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公开(公告)号：US10521271B2
公开(公告)日：2019-12-31
申请号：US15477026
申请日：2017-04-01
Applicant: INTEL CORPORATION
Inventor： Abhishek R Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10430147B2
公开(公告)日：2019-10-01
申请号：US15489096
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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公开(公告)号：US20190272613A1
公开(公告)日：2019-09-05
申请号：US16279270
申请日：2019-02-19
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US20190251655A1
公开(公告)日：2019-08-15
申请号：US16388098
申请日：2019-04-18
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US20190018799A1
公开(公告)日：2019-01-17
申请号：US16113174
申请日：2018-08-27
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , James A. Valerio , Altug Koker , Prasoonkumar P. Surti , Balaji Vembu , Wenyin Fu , Bhushan M. Borole , Kamal Sinha
IPC: G06F12/128 , G06F13/40 , G06F12/0811 , G06T1/20
CPC classification number: G06F12/128 , G06F12/0811 , G06F12/084 , G06F12/0897 , G06F12/12 , G06F13/4022 , G06F2212/1021 , G06F2212/283 , G06F2212/601 , G06F2212/70 , G06T1/60
Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
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Patent Agency Ranking
公开(公告)号：US20180307429A1
公开(公告)日：2018-10-25
申请号：US15493196
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Wenyin Fu , Abhishek R. Appu , Bhushan M. Borole , Altug Koker , Nikos Kaburlasos , Kamal Sinha
IPC: G06F3/06 , G06F12/0897 , G06T1/60 , G06T1/20
CPC classification number: G06F3/0632 , G06F3/0611 , G06F3/0653 , G06F3/0673 , G06F12/0897 , G06F2212/1016 , G06F2212/455 , G06T1/20 , G06T1/60
Abstract: By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.
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公开(公告)号：US20180302064A1
公开(公告)日：2018-10-18
申请号：US15488628
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Anupama A. Thaploo , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
CPC classification number: H03K3/012 , H03K3/35606 , H03K19/215
Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
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公开(公告)号：US20180300951A1
公开(公告)日：2018-10-18
申请号：US15489103
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Wenyin Fu , Nikos Kaburlasos , Jacek Kwiatkowski , Travis T. Schluessler , John H. Feit , Joydeep Ray
Abstract: Methods and apparatus relating to techniques for adaptive tessellation for foveated rendering are described. In one embodiment, a first tessellation operation in a fovea region is performed in accordance with a first tessellation factor and a second tessellation operation in one or more regions surrounding the fovea region in accordance with a second tessellation factor. The first tessellation factor results in a finer tessellation than the second tessellation factor. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180300929A1
公开(公告)日：2018-10-18
申请号：US15488592
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , Altug Koker , Balaji Vembu , Kamal Sinha , Prasoonkumar Surti , Wenyin Fu , Bhushan M. Borole , Vasanth Ranganathan
IPC: G06T15/00 , G06F12/0891 , G06F12/0893
Abstract: In accordance with some embodiments, a separate pipe is used in graphics processor for handling accesses, namely reads, to read only (RO) surfaces within caches. Moreover, the caches may have defined read only section and defined read write (RW) sections. The read only section may be accessed through a dedicated read only pipe and the read write section may be accessed through a read write pipe for those surfaces that can also be written. Thus, the read only sections are handled in a read only fashion without the need to accommodate writes.
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公开(公告)号：US20180300137A1
公开(公告)日：2018-10-18
申请号：US15488947
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Anupama A. Thaploo , Bhushan M. Borole , Bee Ngo , Iqbal R. Rajwani , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
CPC classification number: G06F9/30105 , G06F13/4068 , G06F13/4077 , G11C7/12 , G11C11/4094 , G11C17/16 , G11C17/18
Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.
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