公开(公告)号：US10372362B2

公开(公告)日：2019-08-06

申请号：US15474005

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  John Chun Kwok Leung ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F3/06 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.

公开(公告)号：US20190141120A1

公开(公告)日：2019-05-09

申请号：US16234718

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Timothy Verrall

IPC: H04L29/08

Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.

公开(公告)号：US20190102403A1

公开(公告)日：2019-04-04

申请号：US15719639

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Mark A. Schmisseur ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F17/30

Abstract: Techniques and apparatus for providing access to data in a plurality of storage formats are described. In one embodiment, for example, an apparatus may include logic, at least a portion of comprised in hardware coupled to the at least one memory, to determine a first storage format of a database operation on a database having a second storage format, and perform a format conversion process responsive to the first storage format being different than the second storage format, the format conversion process to translate a virtual address of the database operation to a physical address, and determine a converted physical address comprising a memory address according to the first storage format. Other embodiments are described and claimed.

公开(公告)号：US20190102147A1

公开(公告)日：2019-04-04

申请号：US15719853

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm ,  Mark A. Schmisseur

IPC: G06F7/08 ,  G06F17/30

Abstract: Examples may include a data center in which memory sleds are provided with logic to filter data stored on the memory sled responsive to filtering requests from a compute sled. Memory sleds may include memory filtering logic arranged to receive filtering requests, filter data stored on the memory sled, and provide filtering results to the requesting entity. Additionally, a data center is provided in which fabric interconnect protocols in which sleds in the data center communicate is provided with filtering instructions such that compute sleds can request filtering on memory sleds.

公开(公告)号：US20190095329A1

公开(公告)日：2019-03-28

申请号：US15717825

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Benjamin A. Graniello

IPC: G06F12/0831 ,  G06F12/02 ,  G06F12/1009

Abstract: Technology for a system operable to allocate physical pages of memory is described. The system can include a memory side cache, a memory side cache monitoring unit coupled to the memory side cache, and an operating system (OS) page allocator. The OS page allocator can receive feedback from the memory side cache monitoring unit. The OS page allocator can adjust a page allocation policy that defines the physical pages allocated by the OS page allocator based on the feedback received from the memory side cache monitoring unit.

公开(公告)号：US20180351836A1

公开(公告)日：2018-12-06

申请号：US15613944

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  Rahul Khanna

IPC: H04L12/26 ,  H04L29/08 ,  H04L12/24

Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request related to one or more disaggregated resources, link the one or more disaggregated resources to a local counter, receive performance related data from each of the one or more disaggregated resources, and store the performance related data in the local counter. In an example, the one or more disaggregated resources comprise a software defined infrastructure composite node

公开(公告)号：US20180285009A1

公开(公告)日：2018-10-04

申请号：US15474005

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  John Chun Kwok Leung ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/5044 ,  G06F9/5061

Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.

公开(公告)号：US20180165196A1

公开(公告)日：2018-06-14

申请号：US15375675

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mohan J. Kumar ,  Thomas Willhalm ,  Robert G. Blankenship

IPC: G06F12/0808 ,  G06F13/16 ,  G06F3/06 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/0831 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/128 ,  G06F13/1663 ,  G06F2212/1024 ,  G06F2212/621

Abstract: Embodiments provide for a processor including a cache a caching agent and a processing node to decode an instruction including at least one operand specifying an address range within a distributed shared memory (DSM) and perform a flush to a first of a plurality of memory devices in the DSM at the specified address range.

公开(公告)号：US09983996B2

公开(公告)日：2018-05-29

申请号：US14965487

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Brian Slechta

IPC: G06F12/123 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/084 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/12 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/2542 ,  G06F2212/314 ,  G06F2212/621

Abstract: Technologies for managing cache memory of a processor in a distributed shared memory system includes managing a distance value and an age value associated with each cache line of the cache memory. The distance value is indicative of a distance of a memory resource, relative to the processor, from which data stored in the corresponding chance line originates. The age value is based on the distance value and the number of times for which the corresponding cache line has been considered for eviction since a previous eviction of the corresponding cache line. Initially, the age value is set to the distance value. Additionally, every time a cache line is accessed, the age value associated with the accessed cache line is reset to the corresponding distance value. During a cache eviction operation, the cache line for eviction is selected based on the age value associated with each cache line. The age values of cache lines not selected for eviction are subsequently decremented such that even cache lines associated with remote memory resources will eventually be considered for eviction if not recently accessed.

公开(公告)号：US20180101482A1

公开(公告)日：2018-04-12

申请号：US15784625

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/1027 ,  G06F12/0862

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.