公开(公告)号：US20190181265A1

公开(公告)日：2019-06-13

申请号：US16321356

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/092

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

公开(公告)号：US10229991B2

公开(公告)日：2019-03-12

申请号：US15505911

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/06

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20190058041A1

公开(公告)日：2019-02-21

申请号：US16079337

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L21/8238

Abstract: A gallium nitride transistor can include a silicon substrate and a first oxide layer and a second oxide layer on the substrate. A first gallium nitride layer may reside on the silicon substrate and the first and second oxide layers. A polarization layer may reside on the first gallium nitride layer. A two dimensional electron gas may exist in the first gallium nitride layer proximate to the polarization layer. A second gallium nitride layer may reside on a first sidewall of the polarization layer and on the first oxide layer on the substrate. A first p-doped gallium nitride layer may reside on the second gallium nitride layer. A third gallium nitride layer may reside on a second sidewall of the polarization layer and on the second oxide layer on the substrate. A second p-doped gallium nitride layer may reside on the second gallium nitride layer.

公开(公告)号：US10134727B2

公开(公告)日：2018-11-20

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L29/00 ,  H01L27/06 ,  H01L29/94 ,  H01L29/04 ,  H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8252 ,  H01L21/8258

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

公开(公告)号：US10096682B2

公开(公告)日：2018-10-09

申请号：US15464931

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sherry Taft ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L27/108 ,  H01L29/20 ,  H01L21/02 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

公开(公告)号：US10096474B2

公开(公告)日：2018-10-09

申请号：US15604550

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Niti Goel ,  Sanaz K. Gardner ,  Pragyansri Pathi ,  Matthew V. Metz ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  James M. Powers ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: G06Q30/02 ,  H01L21/02 ,  H01L21/762 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/267 ,  H01L29/165 ,  H01L21/8258 ,  H01L27/092

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US10032911B2

公开(公告)日：2018-07-24

申请号：US15499794

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. Chau ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz Gardner ,  Ravi Pillarisetty

IPC: H01L29/20 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/205 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/34

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US09972686B2

公开(公告)日：2018-05-15

申请号：US15121745

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Willy Rachmady ,  Roza Kotlyar ,  Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros

IPC: H01L21/70 ,  H01L29/161 ,  H01L27/11 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.

公开(公告)号：US09935191B2

公开(公告)日：2018-04-03

申请号：US15122627

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Sansaptak Dasgupta ,  Alejandro X. Levander ,  Patrick Morrow

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/78 ,  H01L29/04 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

公开(公告)号：US09905651B2

公开(公告)日：2018-02-27

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niti Goel ,  Van H. Le ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Stephen M. Cea ,  Robert S. Chau

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.