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公开(公告)号：US10826710B2
公开(公告)日：2020-11-03
申请号：US16682635
申请日：2019-11-13
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj R. Sastry
Abstract: Technologies for elliptic curve cryptography (ECC) include a computing device having an ECC engine that reads one or more parameters from a data port. The ECC engine performs operations using the parameters, such as an Elliptic Curve Digital Signature Algorithm (ECDSA). The ECDSA may be performed in a protected mode, in which the ECC engine will ignore inputs. The ECC engine may perform the ECDSA in a fixed amount of time in order to protect against timing side-channel attacks. The ECC engine may perform the ECDSA by consuming a uniform amount of power in order to protect against power side-channel attacks. The ECC engine may perform the ECDSA by emitting a uniform amount of electromagnetic radiation in order to protect against EM side-channel attacks. The ECC engine may perform the ECDSA verify with 384-bit output in order to protect against fault injection attacks.
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公开(公告)号：US20190325166A1
公开(公告)日：2019-10-24
申请号：US16456339
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Rafael Misoczki , Santosh Ghosh , Raghavan Kumar , Manoj Sastry , Andrew H. Reinders
Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
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公开(公告)号：US20190319802A1
公开(公告)日：2019-10-17
申请号：US16456004
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： RAFAEL MISOCZKI , Santosh Ghosh , Manoj Sastry , David Wheeler
Abstract: In one example an apparatus comprises a computer readable memory to store a public key associated with a signing device, communication logic to receive, from the signing device, a signature chunk which is a component of a signature generated by a hash-based signature algorithm, and at least a first intermediate node value associated with the signature chunk, verification logic to execute a first hash chain beginning with the signature chunk to produce at least a first computed intermediate node value, execute a second hash chain beginning with the at least one intermediate node value associated with the signature chunk to produce a first computed final node value, and use the first computed intermediate node value and the first computed final computed node value to validate the signature generated by the hash-based signature algorithm. Other examples may be described.
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公开(公告)号：US20190319787A1
公开(公告)日：2019-10-17
申请号：US16456096
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： ANDREW H. REINDERS , Santosh Ghosh , Manoj Sastry , Rafael Misoczki
Abstract: In one example an apparatus comprises an unsatisfied parity check (UPC) memory, an unsatisfied parity check (UPC) compute block communicatively coupled to the UPC memory, a first error memory communicatively coupled to the UPC compute block, a polynomial multiplication syndrome memory, a polynomial multiplication compute block communicatively coupled to the polynomial multiplication syndrome memory, a second error memory communicatively coupled to the polynomial multiplication compute block, a codeword memory communicatively coupled to the UPC compute block and the polynomial multiplication compute block, a multiplexer communicatively coupled to first error memory and to the polynomial multiplication compute block, and a controller communicatively coupled to the UPC memory, the polynomial multiplication syndrome memory, the codeword memory, and the multiplexer. Other examples may be described.
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公开(公告)号：US10404468B2
公开(公告)日：2019-09-03
申请号：US15351606
申请日：2016-11-15
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj R. Sastry , Jesse Walker , Li Zhao , Rafael Misoczki
Abstract: Technologies for counter with CBC-MAC (CCM) mode encryption include a computing device that performs a CBC-MAC authentication operation on a message with an encryption key, using a 64-bit block cipher to generate a message authentication code. The computing device generates a first 64-bit authentication block including an 8-bit flag field and a length field of between 11 and 32 bits. The flag field indicates the length of the length field. Performing the CBC-MAC authentication operation includes formatting the message into one or more 64-bit authentication blocks. The computing device performs a counter mode encryption operation on the message with the encryption key using the 64-bit block cipher to generate a cipher text. Performing the counter mode encryption includes generating multiple 64-bit keystream blocks. The computing device generates an authentication tag based on the message authentication code and a first keystream block of keystream blocks. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20190052654A1
公开(公告)日：2019-02-14
申请号：US16026413
申请日：2018-07-03
Applicant: Intel Corporation
Inventor： Marcio Juliato , Shabbir Ahmed , Santosh Ghosh , Manoj R. Sastry
Abstract: A data processing system that provides for active prevention of masquerading attacks comprises a microcontroller, a transceiver, and an active attack prevention module (AAPM) in communication with the microcontroller and the transceiver. The microcontroller enables the data processing system to operate as a node in a vehicle control system (VCS). The transceiver enables the node to communicate with a local area network (LAN) of the VCS. The AAPM enables the node to monitor the LAN for messages. In response to detecting a message on the LAN, the AAPM automatically determines whether the message falsely identifies the node as a source, based on a value in an identifier field in the message. In response to determining that the message falsely identifies the node as the source, the AAPM automatically takes at least one remedial action to neutralize the message. Other embodiments are described and claimed.
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公开(公告)号：US20180091309A1
公开(公告)日：2018-03-29
申请号：US15277462
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Steffen Schulz , Manoj R. Sastry , Santosh Ghosh , Li Zhao
IPC: H04L9/32
CPC classification number: H04L9/3247 , H04L9/3242 , H04L9/3252 , H04L2209/30 , H04L2209/38
Abstract: One embodiment provides a signer device. The signer device includes hash signature control logic and signer signature logic. The hash signature control logic is to retrieve a first nonce, to concatenate the first nonce and a message to be transmitted and to determine whether a first message representative satisfies a target threshold. The signer signature logic is to generate a first transmitted signature based, at least in part, on the first message representative, if the first message representative satisfies the target threshold. The hash signature control logic is to retrieve a second nonce, concatenate the second nonce and the message to be transmitted and to determine whether a second message representative satisfies the target threshold, if the first message representative does not satisfy the target threshold.
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公开(公告)号：US20170187530A1
公开(公告)日：2017-06-29
申请号：US14757658
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj R. Sastry
CPC classification number: H04L9/3066 , G06F7/725 , G09C1/00 , H04L9/14 , H04L2209/12 , H04L2209/24
Abstract: Embodiments of a system for, and method for using, an elliptic curve cryptography integrated circuit are generally described herein. An elliptic curve cryptography (ECC) operation request may be received. One of a plurality of circuit portions may be instructed to perform the ECC operation. The plurality of circuit portions that may be used include a finite field arithmetic circuit portion, an EC point addition and doubler circuit portion, a finite field exponentiation circuit portion, and a point multiplier circuit portion. The result of the ECC operation may then be output.
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公开(公告)号：US09118482B2
公开(公告)日：2015-08-25
申请号：US14039997
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Santosh Ghosh
CPC classification number: H04L9/3066 , G06F12/1408 , H04L9/004
Abstract: A fault tolerant apparatus and method for elliptic curve cryptography. For example, one embodiment of a processor includes one or more cores to execute instructions and process data; and fault attack logic to ensure that the execution of the instructions and processing of the data is not vulnerable to memory safe-error attacks after a fault is injected by hiding any correlation between processor behavior and secret bits in a secret key.
Abstract translation: 椭圆曲线密码学的容错装置和方法。 例如，处理器的一个实施例包括执行指令和处理数据的一个或多个核心; 和故障攻击逻辑，以确保在通过隐藏处理器行为和秘密密钥中的秘密位之间的任何相关性来注入故障之后，指令的执行和数据的处理不易受到内存安全错误攻击的影响。
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90.发明授权公开(公告)号：US12254203B2
公开(公告)日：2025-03-18
申请号：US18145095
申请日：2022-12-22
Applicant: Intel Corporation
Inventor： Sergej Deutsch , Christoph Dobraunig , Rajat Agarwal , David M. Durham , Santosh Ghosh , Karanvir Grewal , Krystian Matusiewicz
Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.
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