公开(公告)号：US20190042350A1

公开(公告)日：2019-02-07

申请号：US15940779

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sundar Nadathur ,  Pratik M. Marolia ,  Henry M. Mitchel ,  Joseph J. Grecco ,  Utkarsh Y. Kakaiya ,  David A. Munday

IPC: G06F11/07 ,  G06F1/02 ,  G06F1/04 ,  G06F1/24 ,  G06F1/26

Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

公开(公告)号：US09935638B1

公开(公告)日：2018-04-03

申请号：US15628888

申请日：2017-06-21

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Joshua D. Fender

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17768 ,  H03K19/17728 ,  H03K19/17764

Abstract: A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.