公开(公告)号：WO2013044257A1

公开(公告)日：2013-03-28

申请号：PCT/US2012/056957

申请日：2012-09-24

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich J. ,  CODRESCU, Lucian

Inventor： PLONDKE, Erich J. ,  CODRESCU, Lucian

IPC: G06F9/48

CPC classification number: G06F9/4856

Abstract: A system and method for memory coherency acceleration via virtual machine migration comprises a plurality of processors. A first processor of the plurality of processors is configured to implement at least one virtual machine. A monitor is configured to monitor a number of memory requests between the first processor and at least a second processor of the plurality of processors. A virtual machine manager is configured to migrate at least a portion of the virtual machine from the first processor to the second processor based on the number of memory requests exceeding a threshold.

Abstract translation: 通过虚拟机迁移的用于存储器一致性加速的系统和方法包括多个处理器。 多个处理器中的第一处理器被配置为实现至少一个虚拟机。 监视器被配置为监视第一处理器与多个处理器中的至少第二处理器之间的多个存储器请求。 虚拟机管理器被配置为基于超过阈值的存储器请求的数量将虚拟机的至少一部分从第一处理器迁移到第二处理器。

公开(公告)号：WO2013044256A1

公开(公告)日：2013-03-28

申请号：PCT/US2012/056956

申请日：2012-09-24

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich J. ,  INGLE, Ajay A. ,  CODRESCU, Lucian

Inventor： PLONDKE, Erich J. ,  INGLE, Ajay A. ,  CODRESCU, Lucian

IPC: G06F9/38

CPC classification number: G06F9/3834 ,  G06F9/3851 ,  G06F9/3853

Abstract: In a particular embodiment, a very long instruction word (VLIW) processor is operable to execute VLIW instructions. At least one of the VLIW instructions includes a first load or store instruction and a second load or store instruction. The first instruction and the second instruction are executed as a single atomic unit. At least one of the first and second instructions is a store-conditional instruction.

Abstract translation: 在特定实施例中，非常长的指令字（VLIW）处理器可操作以执行VLIW指令。 至少一个VLIW指令包括第一加载或存储指令以及第二加载或存储指令。 第一条指令和第二条指令作为一个原子单位执行。 第一和第二指令中的至少一个是存储条件指令。

公开(公告)号：WO2013036950A1

公开(公告)日：2013-03-14

申请号：PCT/US2012/054496

申请日：2012-09-10

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao ,  TABONY, Charles J. ,  VENKUMAHANTI, Suresh K.

Inventor： PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao ,  TABONY, Charles J. ,  VENKUMAHANTI, Suresh K.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/38 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3853

Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.

Abstract translation: 一种装置包括处理器和耦合到处理器的存储器。 存储器存储包括第一谓词独立指令和第二谓词独立指令的指令分组（例如，VLIW指令分组）。 每个谓词独立指令具有相同的目的地。

公开(公告)号：WO2013033709A1

公开(公告)日：2013-03-07

申请号：PCT/US2012/053682

申请日：2012-09-04

Applicant: QUALCOMM INCORPORATED ,  KOOB, Christopher Edward ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  BAYERDORFFER, Bryan C.

Inventor： KOOB, Christopher Edward ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  BAYERDORFFER, Bryan C.

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/0815 ,  G06F12/1081 ,  G06F2212/151 ,  G06F2212/621 ,  G06F2213/0058 ,  Y02D10/13 ,  Y02D10/14

Abstract: A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.

Abstract translation: 一种方法包括选择性地将物理地址路由到发起设备，而不是在管理设备虚拟地址到物理地址的转换的控制器处的共享存储器。 物理地址对应于来自虚拟设备的数据访问。 该方法可以在实现虚拟化输入/输出的计算系统处提供局部一致性。

公开(公告)号：WO2012151331A1

公开(公告)日：2012-11-08

申请号：PCT/US2012/036196

申请日：2012-05-02

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  TABONY, Charles Joseph ,  VENKUMAHANTI, Suresh K. ,  INGLE, Ajay Anant

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  TABONY, Charles Joseph ,  VENKUMAHANTI, Suresh K. ,  INGLE, Ajay Anant

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30167

Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Abstract translation: 程序通常需要不能以本机指令格式编码的常量，例如32位。 为了提供扩展常数，形成具有恒定扩展器信息和目标指令的指令包。 编码为恒定扩展器指令的恒定扩展器信息提供第一组常量位，例如26位，目标指令提供第二组常数位，例如6位。 第一组常数位与第二组常数位组合以产生用于执行目标指令的扩展常数。 扩展常数可以用作扩展源操作数，存储器访问指令的扩展地址，分支类型的指令的扩展地址等。 多个恒定扩展器指令可以一起使用以提供比单个扩展指令可以提供的更大的常数。

公开(公告)号：WO2011088370A1

公开(公告)日：2011-07-21

申请号：PCT/US2011/021368

申请日：2011-01-14

Applicant: QUALCOMM Incorporated ,  VENKUMAHANTI, Suresh K. ,  KOOB, Christopher Edward ,  CODRESCU, Lucian

Inventor： VENKUMAHANTI, Suresh K. ,  KOOB, Christopher Edward ,  CODRESCU, Lucian

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0811 ,  G06F12/0884

Abstract: A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.

Abstract translation: 公开了一种从二级存储器或一级存储器的一部分访问数据的系统和方法。 在特定实施例中，系统包括一级缓存和二级存储器。 二级存储器的第一部分耦合到输入端口，并且可与第一级缓存并行地寻址。

公开(公告)号：WO2010144832A1

公开(公告)日：2010-12-16

申请号：PCT/US2010/038355

申请日：2010-06-11

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  INGLE, Ajay Anant

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  INGLE, Ajay Anant

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/127

Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

Abstract translation: 在特定实施例中，电路设备包括被配置为接收虚拟地址并将虚拟地址转换为具有至少两个分区的高速缓存的物理地址的翻译后备缓冲器（TLB）。 电路装置还包括控制逻辑电路，其适于基于分区指示符来识别与所识别的至少两个分区中的一个分区相关联的分区替换策略。 控制逻辑电路响应于高速缓存未命中事件，根据所识别的分区替换策略来控制高速缓存内的数据的替换。

公开(公告)号：WO2009108462A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/032919

申请日：2009-02-03

Applicant: QUALCOMM INCORPORATED ,  VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian ,  WANG, Lin

Inventor： VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian ,  WANG, Lin

IPC: G06F9/34 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3885

Abstract: In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.

Abstract translation: 在一个实施例中，公开了一种方法，其包括：在执行单元的回写阶段期间，将与将被写入寄存器文件的结果相关联的写入标识符从执行第一指令到与第一指令相关联的读取标识符进行比较 在具有多个执行单元的交错多线程（IMT）处理器内的执行流水线处的第二指令。 当写入标识符与读取标识符匹配时，该方法还包括将结果存储在执行单元的本地存储器中，供执行单元在随后的读取阶段中使用。

公开(公告)号：WO2009073722A1

公开(公告)日：2009-06-11

申请号：PCT/US2008/085402

申请日：2008-12-03

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich J. ,  VENKUMAHANTI, Suresh K

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich J. ,  VENKUMAHANTI, Suresh K

IPC: G06F9/52 ,  G06F12/10

CPC classification number: G06F9/526 ,  G06F9/30083 ,  G06F9/30101 ,  G06F12/1027 ,  G06F2209/522 ,  Y02D10/13

Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.

Abstract translation: 公开了包括具有锁定指示器的多线程处理器的系统和方法。 在一个实施例中，系统包括用于指示多线程处理器中的共享资源的锁定状态的装置。 该系统包括用于在处理与共享资源相关联的异常处理指令之前自动锁定共享资源的装置。 系统还包括用于解锁共享资源的装置。

公开(公告)号：WO2009067525A1

公开(公告)日：2009-05-28

申请号：PCT/US2008/084049

申请日：2008-11-19

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  INGLE, Ajay, A. ,  KOOB, Christopher, E. ,  PLONDKE, Erich, J.

Inventor： CODRESCU, Lucian ,  INGLE, Ajay, A. ,  KOOB, Christopher, E. ,  PLONDKE, Erich, J.

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F13/161

Abstract: A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.

Abstract translation: 公开了用于选择性地排除总线访问请求的系统和方法。 在一个实施例中，一种方法包括确定处理器的逻辑电路处的总线单元访问设置。 该方法还包括基于总线单元访问设置选择性地排除总线单元访问请求。