公开(公告)号：JP2007258366A

公开(公告)日：2007-10-04

申请号：JP2006079239

申请日：2006-03-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KIMURA YASUKI ,  SANHONGI SHOJI ,  TANAKA SATOSHI ,  KIYOU SUIGEN

IPC: H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide a patterning method capable of appropriately grouping the patterns in the same layer.
SOLUTION: This patterning method comprises the step S11 of preparing a pattern layout having a plurality of hole patterns; the step S13 of setting a grid having a plurality of vertical lines and a plurality of horizontal lines on the pattern layout; the step S15 of extracting the nearest vertical line and the nearest horizontal line relating to each hole pattern; the step S17 of judging for each hole pattern whether the first condition is satisfied that both of the extracted vertical line and horizontal line are even lines or both of them are odd lines, or the second condition is satisfied that one of the extracted vertical line and horizontal line is even line and the other is odd line; and the steps S18, S19 of grouping the hole patterns included in the pattern layout into two groups, based on the judgement result.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够适当地分组同一层中的图案的图案化方法。 解决方案：该图案化方法包括准备具有多个孔图案的图案布局的步骤S11; 在图案布局上设置具有多条垂直线和多条水平线的网格的步骤S13; 提取与每个孔图案相关的最近的垂直线和最近的水平线的步骤S15; 判断每个孔图案的步骤S17是否满足第一条件是提取的垂直线和水平线都是偶数行，或者两者都是奇数行，或者第二条件满足提取的垂直线和 水平线是偶数线，另一条是奇数线; 以及基于判断结果将包括在图案布局中的孔图案分组成两组的步骤S18，S19。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007081539A

公开(公告)日：2007-03-29

申请号：JP2005263849

申请日：2005-09-12

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： IISHIRO KATSUMI ,  OGISHIMA SHINJI ,  TANAKA SATOSHI ,  YANAKA YASUHIRO ,  OGINO TAKAHISA

IPC: H04L9/08 ,  H04L9/32

Abstract: PROBLEM TO BE SOLVED: To secure information certainly even if the information is shared by performing communication directly among other devices.
SOLUTION: The gateway unit 10 performs the transmission/reception of data among other devices by controlling communication through a plurality of communication networks connected by an interface corresponding to a plurality of different communication networks by a communication class section 23 and a CORBA section 26. The gateway unit 10 receives data from an IO device 12 and the like, and stores them in the data object of a memory 22. A data manager section 20 stores update information obtained by updating the data in an update information storage section 20a, transmits the update information to the other device through the communication network connected by the interface, and receives the update information from the other device through the communication network, thus updating the data. The communication class section 23 makes an encryption/decryption processing section 24 perform the encryption/decryption of data transmitted/received among the other devices by using a common key for an information sharing group received from an authentication server 8 by an authentication processing section 25.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：即使通过直接在其他设备之间进行通信来共享信息，也可以肯定地确保信息。 解决方案：网关单元10通过通过由通信类部分23和CORBA部分23对与多个不同通信网络相对应的接口连接的多个通信网络进行控制来进行其他设备之间的数据的发送/接收 网关单元10从IO设备12等接收数据，并将其存储在存储器22的数据对象中。数据管理部20存储通过更新数据而获得的更新信息到更新信息存储部20a中， 通过由接口连接的通信网络将更新信息发送给其他设备，并且通过通信网络从其他设备接收更新信息，从而更新数据。 通信类部分23使加密/解密处理部分24通过认证处理部分25使用从认证服务器8接收的用于信息共享组的公共密钥来执行其他设备之间发送/接收的数据的加密/解密。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007081538A

公开(公告)日：2007-03-29

申请号：JP2005263848

申请日：2005-09-12

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： IISHIRO KATSUMI ,  OGISHIMA SHINJI ,  TANAKA SATOSHI ,  YANAKA YASUHIRO ,  OGINO TAKAHISA

IPC: H04L12/66 ,  H04M11/00

Abstract: PROBLEM TO BE SOLVED: To share data among other devices connected with a plurality of different communication networks.
SOLUTION: This gateway unit 10 is provided with an interface (wireless device I/F card 33, portable telephone I/F card 34, satellite communication I/F card 35, wireless LAN card 36) for connection with a plurality of different communication networks. Each section (communication class section 24, CORBA section 26) of the gateway unit 10 performs the transmission/reception of data among other devices by controlling communication through the plurality of different communication networks connected by the interface. The gateway unit 10 receives data from an IO device 12 and the like, and stores the data in the data object of a memory 22. A data manager section 20 stores update information obtained by updating the data in an update information storage section 20a, transmits the update information to the other device through the communication network connected by the interface, and receives the update information from the other device through the communication network, thus updating the data.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：在与多个不同的通信网络连接的其他设备之间共享数据。 解决方案：该网关单元10设置有用于与多个网络连接的接口（无线设备I / F卡33，便携式电话I / F卡34，卫星通信I / F卡35，无线LAN卡36） 不同的通信网络。 网关单元10的每个部分（通信类别部分24，CORBA部分26）通过控制通过该接口连接的多个不同通信网络的通信来执行其他设备之间的数据的发送/接收。 网关单元10从IO设备12等接收数据，并将数据存储在存储器22的数据对象中。数据管理部20存储通过更新数据而获得的更新信息，在更新信息存储部20a中发送 通过由该接口连接的通信网络向其他设备提供更新信息，并且通过通信网络从其他设备接收更新信息，从而更新数据。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006318978A

公开(公告)日：2006-11-24

申请号：JP2005137423

申请日：2005-05-10

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： DEWA KYOKO ,  MINAMI FUMIHIRO ,  UEDA TOSHIAKI ,  OGAWA RYUJI ,  TANAKA SATOSHI

IPC: H01L21/82 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5068 ,  G06F17/5031 ,  G06F17/5036

Abstract: PROBLEM TO BE SOLVED: To reduce a load of timing closure on design side and a load of OPC and process verification on manufacture side, and to improve design efficiency. SOLUTION: The pattern design method is used to design a pattern of a semiconductor circuit, and it includes steps 11 and 12 to prepare a design pattern cells arranged and wired in unit of a function block of a semiconductor circuit; step 13 to analyze the electrical property of a circuit corresponding to the design pattern; a step 14 to create a mask pattern data on the basis of the design pattern in case when the analysis result of the electrical property satisfies the predetermined electrical characteristic; a step 15 to find out an mount of deviation between a pattern of a mask pattern formed on a wafer and an estimated pattern; and a step to correct at least either of the arrangement and the wiring of the cell of the design pattern corresponding to the mask pattern, in case when the amount of deviation is larger than the predetermined allowable amount of variation. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：减少设计侧的定时关闭负载，OPC负载和制造方的过程验证，并提高设计效率。 解决方案：图案设计方法用于设计半导体电路的图案，其包括步骤11和12，以准备以半导体电路的功能块为单位布置和布线的设计图案单元; 步骤13，分析对应于设计图案的电路的电特性; 在电特性的分析结果满足预定的电特性的情况下，基于设计图案创建掩模图案数据的步骤14; 步骤15，找出在晶片上形成的掩模图案的图案与估计图案之间的偏差的位置; 以及在偏差量大于预定允许变化量的情况下，校正与掩模图案相对应的设计图案的单元的布置和布线中的至少一个的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006108510A

公开(公告)日：2006-04-20

申请号：JP2004295268

申请日：2004-10-07

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SUGIMAE KIKUKO ,  ICHIGE MASAYUKI ,  HASHIMOTO KOJI ,  TANAKA SATOSHI

IPC: H01L21/8247 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

Abstract: PROBLEM TO BE SOLVED: To form a borderless contact for word lines or a via-contact for bit lines with a high yield by utilizing partially removed wiring patterns. SOLUTION: The semiconductor memory device comprises a plurality of active region patterns AA i , AA i+1 , ..., AA n extending in the direction of columns on a memory cell array; a plurality of word line patterns WL1, WL2 extending in the direction of rows and disposed non-uniformly; a plurality of selection gate line patterns SG1, SG2 arrayed in parallel with the plurality of word line patterns; a borderless contact 14 disposed in the vicinity of a terminal of the word line pattern on the memory cell array, contacting a part of wiring pulled out of the end of the memory cell array and not contacting with wiring adjacent to the wiring; and a bit line contact (CB) 11 disposed within a region planned to form the contact formed by removing, by means of double exposure, a part of the plurality of word line patterns and selection gate line patterns. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过利用部分去除的布线图案，以高产率形成用于字线或位线的通孔接触的无边界接触。 解决方案：半导体存储器件包括多个有源区域图案AA，SB，i，B，...， >在存储单元阵列上的列的方向上延伸; 沿行方向延伸并且非均匀布置的多个字线图案WL1，WL2; 与多个字线图案并行排列的多个选择栅极线图案SG1，SG2; 设置在存储单元阵列上的字线图案的端子附近的无边界触点14，与从存储单元阵列的端部拉出而不与布线相邻的布线接触的一部分布线接触; 以及布置在计划形成通过双重曝光的多个字线图案的一部分和选择栅线图案形成的接触的区域内的位线接触（CB）11。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006058464A

公开(公告)日：2006-03-02

申请号：JP2004238535

申请日：2004-08-18

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NOJIMA SHIGEKI ,  MOTOKI HIROSHI ,  IKEDA TAKAHIRO ,  TANAKA SATOSHI ,  ITO KENJI

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  H01L21/82

CPC classification number: G03F1/84

Abstract: PROBLEM TO BE SOLVED: To provide a method for measuring a pattern which allows the automatization of pattern measurement.
SOLUTION: The method for measuring a pattern includes a step S1 for preparing a substrate having a pattern, a step S4 for extracting a part to be measured on the substrate based on the simulation using the pattern data concerned with the pattern as input data, a step S6 for forming informations for measuring physical quantities of the extracted part to be measured, and a step 10 for measuring the extracted part to be measured based on the informations by a measuring means.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于测量允许图案测量自动化的图案的方法。 解决方案：用于测量图案的方法包括用于制备具有图案的基板的步骤S1，用于基于使用与图案相关的图案作为输入的图案数据的模拟在基板上提取待测量的部分的步骤S4 数据，用于形成用于测量所提取的被测量部件的物理量的信息的步骤S6，以及基于测量装置的信息测量所提取的待测部分的步骤10。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005181524A

公开(公告)日：2005-07-07

申请号：JP2003419601

申请日：2003-12-17

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： KOTANI TOSHIYA ,  NOJIMA SHIGEKI ,  KIYOU SUIGEN ,  DEWA KYOKO ,  OGAWA RYUJI ,  TANAKA SATOSHI ,  INOUE SOICHI ,  ICHIKAWA HIROTAKA

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82 ,  G03F1/08

CPC classification number: G06F17/5081 ,  H01L21/0271

Abstract: PROBLEM TO BE SOLVED: To automatically obtain an optimum layout with the smallest layout area which is free of a dangerous pattern under given process conditions.
SOLUTION: A design layout generating method of generating an optimum design layout with given semiconductor process parameters by repeatedly optimizing at least one of a design rule, a process proximity effect correction parameter, and a semiconductor process parameter, comprises: calculating finish plane shapes on a wafer with a plurality of process parameters respectively; calculating evaluation values from the finish plane shapes; deciding whether or not the respective calculated evaluation values satisfy tolerance; calculating position coordinates and evaluation values when the tolerance is not satisfied; generating a design layout alteration guideline on the basis of the calculated position coordinates and the evaluation values; and partially correcting the design layout on the basis of the generated design layout alteration guideline.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：在给定的工艺条件下，自动获得最小布局区域，该布局区域不含危险图案。 解决方案：通过重复优化设计规则，过程接近效应校正参数和半导体工艺参数中的至少一个来生成具有给定半导体工艺参数的最佳设计布局的设计布局生成方法包括：计算完成面 分别具有多个工艺参数的晶片上的形状; 从平面形状计算评估值; 判定各计算出的评价值是否满足公差; 当不满足公差时，计算位置坐标和评估值; 根据计算出的位置坐标和评估值生成设计布局变更指南; 并在生成的设计布局变更指南的基础上部分纠正设计布局。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005129648A

公开(公告)日：2005-05-19

申请号：JP2003362145

申请日：2003-10-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SANHONGI SHOJI ,  NAKAMURA HIROKO ,  INOUE SOICHI ,  FUKUHARA KAZUYA ,  TANAKA SATOSHI

IPC: G03F7/26 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC classification number: G03F7/70425 ,  G03F7/70466 ,  H01L21/76816

Abstract: PROBLEM TO BE SOLVED: To form a contact hole at a low cost although a resolution in a crowded part is assured highly.
SOLUTION: A method of forming a contact hole includes a step of exposing and developing a first photosensitive resist film on a substrate by using a photomask having mask patterns disposed periodically in a first direction and a second direction intersecting perpendicularly with the first direction and double lighting, a step of forming a first line and space along the first direction, thereafter a step of forming a second photosensitive region on the substrate, a step of exposing and developing the second photosensitive resist film by using the photomask and the double lighting intersecting perpendicularly with the double illuminating, and a step of forming a second line and space intersecting perpendicularly with the first line and space.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：尽管高密度地确保了拥挤部分中的分辨率，但是以低成本形成接触孔。 解决方案：形成接触孔的方法包括通过使用具有沿第一方向周期性地设置的掩模图案的光掩模和与第一方向垂直相交的第二方向的曝光和显影基板上的第一光敏抗蚀剂膜的步骤 和双重照明，沿着第一方向形成第一线和空间的步骤，此后在基板上形成第二感光区域的步骤，通过使用光掩模和双光照曝光和显影第二光敏抗蚀剂膜的步骤 与双重照明垂直相交，以及形成与第一线和空间垂直相交的第二线和空间的步骤。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005084101A

公开(公告)日：2005-03-31

申请号：JP2003312745

申请日：2003-09-04

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01J37/302 ,  H01L21/027 ,  G03F1/08

CPC classification number: G03F1/36 ,  H01J37/3026 ,  H01J2237/31769

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a mask pattern for reducing the process time of PPC (process proximity correction) without increasing a chip area.
SOLUTION: The method for manufacturing a mask pattern includes steps of: subjecting each of a plurality of cell patterns stored in a first cell library to the process proximity correction to prepare a second cell library to store a plurality of corrected cell patterns; arranging a first corrected cell pattern and a second corrected cell pattern as one of the plurality of corrected cell patterns so that the respective edges are brought into contact with, are adjacent to or are overlapped on each other; extracting the boundary pattern near the boundary of the first corrected cell pattern and the second corrected cell pattern; and subjecting the boundary pattern to the process proximity correction.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于减少PPC的处理时间（工艺接近校正）而不增加芯片面积的掩模图案的方法。 解决方案：用于制造掩模图案的方法包括以下步骤：将存储在第一单元库中的多个单元图案中的每一个进行过程接近校正，以准备第二单元库，以存储多个经校正的单元图形; 将第一校正单元图案和第二校正单元图形布置为多个校正单元图案之一，使得各边缘相互接触或相互重叠; 提取在所述第一校正单元图案和所述第二校正单元图案的边界附近的边界图案; 并对边界图案进行过程接近校正。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004294732A

公开(公告)日：2004-10-21

申请号：JP2003086563

申请日：2003-03-26

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TANAKA SATOSHI ,  HASHIMOTO KOJI

IPC: G03F1/36 ,  G03F1/68 ,  G03F7/00 ,  G03F7/20 ,  G03F9/00 ,  G06F17/50 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  G03F1/08

CPC classification number: H01L21/0274 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/31144 ,  H01L21/32139

Abstract: PROBLEM TO BE SOLVED: To provide a mask set for forming a pattern having both of smaller line width than the optically resolvable minimum line width of a projection exposure apparatus and the optically resolvable minimum space width of the projection exposure apparatus. SOLUTION: The mask set aims to form a fine line part having smaller line width than the optically resolvable minimum line width of the projection exposure apparatus on an exposure substrate by preliminarily thinning the line width of the pattern after exposure. The mask set includes (1) a first mask 10 having fine line patterns 11a 11b for forming the fine line part and (2) a second mask having a window to remove an unnecessary part from the pattern formed by the first mask 10. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成具有比投影曝光装置的光学可分辨最小线宽度小的线宽的图案的掩模组和投影曝光装置的光学可分辨的最小空间宽度。 解决方案：掩模组旨在通过预先使曝光后的图案的线宽变薄来形成具有比曝光基板上的投影曝光装置的光学可分辨最小线宽更小的线宽的细线部分。 掩模组包括（1）具有用于形成细线部分的细线图案11a 11b的第一掩模10和（2）具有从第一掩模10形成的图案中除去不必要部分的窗口的第二掩模。

版权所有（C）2005，JPO＆NCIPI