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公开(公告)号：US20240402743A1
公开(公告)日：2024-12-05
申请号：US18678767
申请日：2024-05-30
Applicant: STMicroelectronics International N.V.
Inventor： Helene ESCH , Jerome BOURGOIN , Eric FELTRIN
Abstract: A voltage regulator has a first output is connected to a capacitive element. A current source is coupled between the first output and a first node receiving a power supply voltage. The current source delivers a first DC current in response to assertion of a first binary signal. A comparator asserts a second binary signal when a first voltage on the first output is lower than a set point voltage. A first circuit controls assertion of the first signal for a first fixed time period when the second binary signal is asserted.
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公开(公告)号：US20240402358A1
公开(公告)日：2024-12-05
申请号：US18671027
申请日：2024-05-22
Applicant: STMicroelectronics International N.V.
Inventor： Jerome DURAND , Nicola Matteo PALELLA , Leonardo COLOMBO
Abstract: A device includes global positioning circuitry, sensing circuitry, and processing circuitry. The global positioning circuitry, in operation, receives location-related data. The sensing circuitry, in operation, senses data related to the device. The processing circuitry, in operation, determines a motion state of the electronic system based on data sensed by the sensing circuitry, and selects a plurality of control parameters from one or more configuration matrixes based on the determined motion state. The plurality of control parameters includes a power-mode control parameter and a location-determination control parameter. The processing circuitry configures a power-mode of the device based on the power-mode control parameter, and determines a location characteristic of the device based on the received location-related data and the location-determination control parameter.
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公开(公告)号：US20240396535A1
公开(公告)日：2024-11-28
申请号：US18666532
申请日：2024-05-16
Applicant: STMicroelectronics International N.V.
Inventor： Rohit Kumar GUPTA
Abstract: A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.
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84.发明申请公开(公告)号：US20240393500A1
公开(公告)日：2024-11-28
申请号：US18202418
申请日：2023-05-26
Applicant: STMicroelectronics International N.V.
Abstract: A metasurface optic, designed for short-wave infrared (SWIR) range devices, is formed of one or more unit cells with a specific arrangement of truncated cone-shaped subwavelength nanostructures, tailored to achieve various optical functionalities. The one or more unit cells are formed from a design set selected from among multiple different design sets, each of the multiple different design sets featuring truncated cones having a unique combination of height (800 nm to 1100 nm), sidewall angle (91° to) 93°, and pitch (550 nm to 750 nm), with base radius values of the truncated cones within a given design set varying from 75 nm to 250 nm in 1 nm increments.
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公开(公告)号：US20240385241A1
公开(公告)日：2024-11-21
申请号：US18199065
申请日：2023-05-18
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep JAIN , Pooja JAIN , Esha PAL
IPC: G01R31/317 , G01R31/3183 , G01R31/3185
Abstract: Test circuitry includes a scan-compressor receiving n scan-input bits from n input-pins and compressing those bits for distribution among z scan-chains, z being less than n. A scan-decompressor receives test response data from the scan-chains and decompresses the test response data, reconstructing n scan-output bits. An OCC generates a test-clock based on clock-bits received from a clock-chain, with the test-clock operating the scan-chains and the clock-chain. The clock-chain receives m clock-chain input bits from m of the input-pins, m being less than n, and provides the clock-bits to the OCC for generating the test-clock. The test circuitry performs tests on the IC. Each test is associated with the test-clock generated by the OCC based on a given set of clock-bits. Tests associated with the test-clock generated by the OCC based on the same given set of clock-bits are performed after a single loading of that same given set of clock-bits.
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Patent Agency Ranking
公开(公告)号：US20240383429A1
公开(公告)日：2024-11-21
申请号：US18317795
申请日：2023-05-15
Applicant: STMicroelectronics International N.V.
Inventor： Stefano Paolo RIVOLTA , Federico RIZZARDINI , Marco BIANCO
IPC: B60R21/0132
Abstract: A crash detection system includes first and second sensors and a processor. The processor receives first sensor data output by the first sensor, determines whether the first sensor data indicates a first class or a second class, outputs an enable signal to the second sensor if the first sensor data indicates the second class, receives second sensor data output by the second sensor after the enable signal is output, determines whether the second sensor data indicates a high acceleration value, determines whether the first sensor data indicates the first class within a predetermined amount of time after the second sensor data is determined to indicate the high acceleration value, and outputs a signal indicating a crash has occurred in response to determining that the first sensor data indicates the first class within the predetermined amount of time after the second sensor data is determined to indicate the high acceleration value.
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公开(公告)号：US20240364340A1
公开(公告)日：2024-10-31
申请号：US18627941
申请日：2024-04-05
Applicant: STMicroelectronics International N.V.
Inventor： Manoj Kumar TIWARI , Kailash KUMAR
IPC: H03K19/0185
CPC classification number: H03K19/018521
Abstract: A level shifter having current boosting stages is provided. The level shifter includes a level shifting stage including a plurality of transistors and first and second nodes. The level shifting stage is configured to transfer a first signal of a first voltage domain to a second signal of a second voltage domain. A plurality of current boosting stages are associated with the transistors, respectively. A first current boosting stage provides a first boosting stage current path to support a first level shifter current path of a first transistor of the plurality of transistors in response to: a first supply voltage of the first voltage domain being greater than a second supply voltage of the second voltage domain, the first signal having a first logical state and the first node having a logical state reflecting that the first signal has a second logical state different from the first logical state.
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公开(公告)号：US20240356753A1
公开(公告)日：2024-10-24
申请号：US18636882
申请日：2024-04-16
Applicant: STMicroelectronics International N.V.
Inventor： Quentin Guellaën , Julien Montmasson , Geraud Plagne
CPC classification number: H04L9/3236 , H04L9/0869
Abstract: A process comprises transmitting, by a first device and through a first communication channel, a message comprising an identifier of the first channel, a first encrypted authentication value and at least one encrypted data value, the first authentication value being associated with the first device, receiving, by a second device, the message, decrypting, by a first circuit of the second device, the first encrypted authentication value, applying, by the first circuit of the second device, at least one non-invertible operation on the first decrypted authentication value, resulting in a verification value, comparing, by the first circuit of the second device, the verification value with the identifier of the first channel, and processing the at least one encrypted data value based on the comparison.
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公开(公告)号：US20240356372A1
公开(公告)日：2024-10-24
申请号：US18636829
申请日：2024-04-16
Applicant: STMicroelectronics International N.V.
Inventor： Jean-Louis DEMESSINE , Hughes CREUSY , Renaud LEMONNIER
IPC: H02J50/10
CPC classification number: H02J50/10
Abstract: A wireless communication device receives power in wireless fashion from another wireless communication device. A charging circuit of the wireless communication device is configured to charge a power storage device. A communication circuit of the wireless communication device is configured to communicate information relative to the charging of the power storage device to the other wireless communication device. To accomplish this, the communication circuit includes a wireless communication transponder and a switch coupled to a first terminal of the transponder, wherein the open and closed state of switch is controlled by the charging circuit.
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公开(公告)号：US20240355913A1
公开(公告)日：2024-10-24
申请号：US18637047
申请日：2024-04-16
Applicant: STMicroelectronics International N.V.
Inventor： Pascal CHEVALIER , Nicolas GUITARD
IPC: H01L29/732 , H01L27/06 , H01L29/66
CPC classification number: H01L29/732 , H01L27/0623 , H01L29/66272
Abstract: An electronic device includes a bipolar transistor. A collector of the bipolar transistor is formed by first and second regions. The second region is located between the first region and a base of the bipolar transistor. A conductive element at least partially surrounds and is insulated from the second region. The conductive element is located between the first region and the base.
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