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    PHY Preamble Format For Wireless Communication System
    82.
    发明申请
    PHY Preamble Format For Wireless Communication System 审中-公开
    无线通信系统的PHY前导格式

    公开(公告)号：US20130136063A1

    公开(公告)日：2013-05-30

    申请号：US13751388

    申请日：2013-01-28

    Applicant: Marvell World Trade Ltd.

    Inventor： Hongyuan Zhang ,  Rohit U. Nabar ,  Songping Wu

    IPC: H04W56/00

    CPC classification number: H04W56/001 ,  H04B1/7073 ,  H04B1/70735 ,  H04B2201/7073 ,  H04J13/0014 ,  H04J13/10 ,  H04L5/0016 ,  H04L27/2613 ,  H04L27/262 ,  H04L27/2656 ,  H04L27/2662 ,  H04W56/00

    Abstract: A system and method of extracting data from data packets transmitted over a wireless network includes receiving a data packet having a preamble portion and a payload portion. The preamble portion is cross correlated with a first known spreading sequence to generate a first timing signal and the preamble portion is cross correlated with a second known spreading signal to generate a frame timing signal. An impulse is detected in the first timing signal and a first timing parameter is set based upon the detected impulse in the first timing signal. An impulse is detected in the frame timing signal and a frame timing parameter is set based upon the detected impulse in the frame timing signal. Data is extracted from the received payload portion according to the first timing parameter and the frame timing parameter.

    Abstract translation: 从通过无线网络发送的数据分组中提取数据的系统和方法包括：接收具有前同步码部分和有效载荷部分的数据分组。 前导码部分与第一已知扩展序列交叉相关，以产生第一定时信号，并且前同步码部分与第二已知扩展信号相互相关，以产生帧定时信号。 在第一定时信号中检测到脉冲，并且基于第一定时信号中检测到的脉冲设置第一定时参数。 在帧定时信号中检测到脉冲，并且基于帧定时信号中检测到的脉冲设置帧定时参数。 根据第一定时参数和帧定时参数从接收到的有效载荷部分提取数据。

    CLOCK AND DATA RECOVERY CIRCUIT WITH SPREAD SPECTRUM CLOCKING SYNTHESIZER
    84.
    发明公开
    CLOCK AND DATA RECOVERY CIRCUIT WITH SPREAD SPECTRUM CLOCKING SYNTHESIZER 审中-公开

    公开(公告)号：US20230163765A1

    公开(公告)日：2023-05-25

    申请号：US17902917

    申请日：2022-09-05

    Applicant: MEDIATEK INC.

    Inventor： Chien-Kai Kao ,  Yi-Hsien Cho

    IPC: H03L7/08 ,  H03L7/085 ,  H04L7/033 ,  H04L7/00 ,  H04B1/7073

    CPC classification number: H03L7/0807 ,  H03L7/085 ,  H04L7/0331 ,  H04L7/0025 ,  H04B1/7073 ,  H04B2201/7073

    Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

    Multi-channel transceiver
    90.
    发明授权
    Multi-channel transceiver 有权
    多通道收发器

    公开(公告)号：US09312910B1

    公开(公告)日：2016-04-12

    申请号：US14686993

    申请日：2015-04-15

    Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yen-Chung Chen

    IPC: H04B1/00 ,  H04B1/7085 ,  H04L7/033 ,  H04L7/00

    CPC classification number: H04B15/00 ,  H03M9/00 ,  H04B2201/7073

    Abstract: A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

    Abstract translation: 多通道收发器包括锁相环电路，第一发送信道和第二发送信道。 锁相环电路产生具有不同频率的第一时钟信号组和第二时钟信号。 第一发送信道包括第一相位调整电路和第一发送器。 第一相位调整电路接收第一时钟信号组并产生具有第一SSCG分布的第一扩频时钟信号。 根据第一扩频时钟信号，第一发射机产生第一串行数据。 第二发送信道包括第二相位调整电路和第二发送器。 第二相位调整电路接收第二时钟信号组并产生具有第二SSCG分布的第二扩频时钟信号。 根据第二扩频时钟信号，第二发射机产生第二串行数据。

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