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    Methods and apparatus for low-density parity check decoding using hardware sharing and serial sum-product architecture
    2.
    发明专利
    Methods and apparatus for low-density parity check decoding using hardware sharing and serial sum-product architecture 审中-公开
    使用硬件共享和串行SUM产品架构的低密度奇偶校验解码的方法和装置

    公开(公告)号：JP2014099944A

    公开(公告)日：2014-05-29

    申请号：JP2014044504

    申请日：2014-03-07

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： HARATSCH ERICH F ,  RATNAYAKE RUWAN

    IPC: H03M13/19

    CPC classification number: H03M13/1131 ,  H03M13/1111 ,  H03M13/6566

    Abstract: PROBLEM TO BE SOLVED: To provide methods and apparatus for decoding codes that can be described using bipartite graphs having interconnected bit nodes and check nodes.SOLUTION: A magnitude of a check-to-bit node message from a check node (j) to a bit node (i) is computed based on a sum of transformed magnitudes of bit-to-check node messages for a plurality of bit nodes connected to the check node (j), excluding the transformed magnitude of a bit-to-check node message for the bit node (i) and the check node (j). A positive/negative sign of the check-to-bit node message from the check node (j) to the bit node (i) may also be computed by multiplying a product Sof the positive/negative sign of the bit-to-check node message by the positive/negative sign of the bit-to-check node message for the bit node (i) and the check node (j).

    Abstract translation: 要解决的问题：提供用于解码可以使用具有互连位节点和校验节点的二分图描述的代码的方法和装置。解决方案：从校验节点（j）到校验节点 基于与校验节点（j）连接的多个比特节点的比特到校验节点消息的变换幅度的和来计算比特节点（i），不包括比特到校验节点消息的变换幅度 对于位节点（i）和校验节点（j）。 来自校验节点（j）到比特节点（i）的检查对比特节点消息的正/负号也可以通过将乘积Sof乘以比特到检查节点的正/负号来计算 用于比特节点（i）和校验节点（j）的比特到校验节点消息的正/负号消息。

    Method and apparatus for soft-output viterbi detection using multiple-step trellis
    3.
    发明专利
    Method and apparatus for soft-output viterbi detection using multiple-step trellis 有权
    使用多步TRELLIS软输出检测的方法和装置

    公开(公告)号：JP2013141300A

    公开(公告)日：2013-07-18

    申请号：JP2013047910

    申请日：2013-03-11

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： ASHLEY JONATHAN J ,  FITZPATRICK KELLY KNUDSON ,  HARATSCH ERICH F

    IPC: H03M13/41

    CPC classification number: H03M13/4192 ,  H03M13/395 ,  H03M13/4153

    Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for performing SOVA detection at higher data rates.SOLUTION: A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, where a first path of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle, and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle.

    Abstract translation: 要解决的问题：提供一种用于以较高数据速率执行SOVA检测的方法和装置。解决方案：接收信号通过以下步骤来处理：（i）确定至少三个选择信号，所述选择信号定义通过多步网格的多条路径 给定状态，其中所述多个路径中的第一路径是用于多步网格周期的每个单步网格周期的获胜路径，第二路径是用于第一单步网格周期的获胜路径 并且是多步骤网格周期的第二个单步网格周期的丢失路径，第三个路径是第一个单步网格周期的丢失路径，是第二个单步网格周期的获胜路径， 多步循环的阶梯状周期; 以及（ii）通过多步网格确定与最大似然路径相关联的比特决策的可靠性值，或者确定每个多步网格周期的多个可靠性值。

    Device and method to enhance call center support for mobile communication device
    4.
    发明专利
    Device and method to enhance call center support for mobile communication device 有权
    用于增强移动通信设备的呼叫中心支持的设备和方法

    公开(公告)号：JP2013013150A

    公开(公告)日：2013-01-17

    申请号：JP2012227775

    申请日：2012-10-15

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： LANDSCHAFT ASSAF ,  WOHLSTADTER GAL ,  WOHLSTADTER GIL

    IPC: H04M3/51 ,  H04M1/00 ,  H04M11/00

    CPC classification number: H04M7/0039 ,  G06F3/1454 ,  H04M3/5133 ,  H04M7/009 ,  H04M2201/38 ,  H04M2207/18

    Abstract: PROBLEM TO BE SOLVED: To provide a device and a method to enhance call center support for a mobile communication device.SOLUTION: A method for providing call center support to a mobile communication device is provided. The method in one embodiment comprises: (1) a step of establishing voice and data communication connection between a mobile communication device having a visual display and a call center communication device having a visual display; and (2) a step of causing the entirety of an image appearing on the visual display of the mobile communication device to be replicated on the visual display of the call center communication device.

    Abstract translation: 要解决的问题：提供一种用于增强移动通信设备的呼叫中心支持的设备和方法。 提供了一种用于向移动通信设备提供呼叫中心支持的方法。 一个实施例中的方法包括：（1）在具有视觉显示的移动通信设备和具有视觉显示的呼叫中心通信设备之间建立语音和数据通信连接的步骤; 以及（2）使呼叫中心通信装置的视觉显示器上复制出现在移动通信装置的视觉显示器上的图像的整体的步骤。 版权所有（C）2013，JPO＆INPIT

    Serial protocol for agile sample rate switching
    5.
    发明专利
    Serial protocol for agile sample rate switching 有权
    用于AGILE样本速率切换的串行协议

    公开(公告)号：JP2012249313A

    公开(公告)日：2012-12-13

    申请号：JP2012164502

    申请日：2012-07-25

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： LAU KIN-HON ,  RANSIJN JOHANNES G ,  HAROLD THOMAS SIMMONDS ,  JAMES D YODER

    IPC: H04L7/00

    CPC classification number: H04M3/005 ,  H04L5/1423 ,  H04L25/0266

    Abstract: PROBLEM TO BE SOLVED: To provide a communication protocol and serial interface having an approximately fixed barrier clock and capable of adapting to a variety of communication rates.SOLUTION: The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though a barrier clock rate is kept approximately constant. A method for designing an agile barrier interface is also provided. In particular, the barrier clock rate is preferably selected to be an approximately common multiple of the various communication rates that the barrier interface must handle. A frame length corresponding to each communication rate is obtained by dividing the barrier clock rate by ΣΔ rate. Thus, there is provided an agile communication circuit capable of communicating data through a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

    Abstract translation: 要解决的问题：提供具有近似固定的屏障时钟并能够适应各种通信速率的通信协议和串行接口。 解决方案：即使屏障时钟速率保持近似恒定，该接口也采用可扩展或缩小的可变长度帧以获得所需的通信速率。 还提供了一种用于设计敏捷屏障界面的方法。 特别地，屏障时钟速率优选地被选择为屏障接口必须处理的各种通信速率的近似公倍数。 通过将屏障时钟速率除以ΣΔ率来获得对应于每个通信速率的帧长度。 因此，提供了一种能够以各种数据速率和大致固定的接口时钟速率通过串行接口传送数据的敏捷通信电路。 版权所有（C）2013，JPO＆INPIT

    Integrated circuit including esd circuits for multi-chip module and method therefor
    7.
    发明专利
    Integrated circuit including esd circuits for multi-chip module and method therefor 审中-公开
    集成电路，包括用于多芯片模块的ESD电路及其方法

    公开(公告)号：JP2012186484A

    公开(公告)日：2012-09-27

    申请号：JP2012100569

    申请日：2012-04-26

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： CHITTIPEDDI SAILESH ,  COCHRAN WILLIAM THOMAS ,  IFUDA SUMOOHA

    IPC: H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H02H3/22

    CPC classification number: H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide electrostatic discharge protection for a multi-chip module of an integrated circuit.SOLUTION: An integrated circuit is provided which includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit is coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

    Abstract translation: 要解决的问题：为集成电路的多芯片模块提供静电放电保护。

    解决方案：提供集成电路，其中包含可能受到ESD损伤或不受ESD保护的I / O电路。 可以选择性地禁用或激活对ESD损坏的保护，或者可以在一个或多个I / O电路中完全不存在。 在使用中，集成电路耦合到另一集成电路以形成多芯片模块，其中模块之间的I / O电路的ESD保护被去激活或不存在。 这是有利的，因为一旦形成多芯片模块就可以减少对该I / O电路的ESD损坏的可能性。 应当理解，上述一般描述和以下详细描述都是本发明的示例性的，但不是限制性的。 版权所有（C）2012，JPO＆INPIT

    Semiconductor device barrier layer
    10.
    发明专利
    Semiconductor device barrier layer 审中-公开
    半导体器件屏障层

    公开(公告)号：JP2011205155A

    公开(公告)日：2011-10-13

    申请号：JP2011160546

    申请日：2011-07-22

    Applicant: Agere Systems Inc ,  アギア システムズ インコーポレーテッド

    Inventor： MERCHANT SAILESH M ,  OLADEJI ISAIAH O ,  KOH SEONG JIN

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a barrier layer used for metallization of a semiconductor device component and deactivation of a dielectric material.SOLUTION: The barrier layer for the semiconductor device metallization component provides a silicon nitride film formed in a component recess and a refractory metal film formed over the silicon nitride film. The device component includes the dielectric material and a recess formed in the dielectric. The surface of the dielectric material within the recess is exposed to nitrogen under controlled parameters. A section of the dielectric material adjacent an interior of the recess is converted to silicon nitride. The refractory metal is then conformed deposited along the recess sidewalls. A seed layer is then deposited over the refractory metal film, and a conductive metal is then deposited within the recess. The device is then polished to remove excess metal in the outside of the recess and planarize the device.

    Abstract translation: 要解决的问题：提供用于半导体器件部件的金属化的阻挡层和电介质材料的失活。解决方案：半导体器件金属化部件的阻挡层提供形成在部件凹部中的氮化硅膜和难熔金属 在氮化硅膜上形成膜。 器件部件包括电介质材料和形成在电介质中的凹部。 凹陷内的电介质材料的表面在受控参数下暴露于氮气。 与凹陷内部相邻的电介质材料的一部分被转换为氮化硅。 然后使难熔金属沿着凹陷侧壁成一定的沉积。 然后将种子层沉积在难熔金属膜上，然后在凹槽内沉积导电金属。 然后将该装置抛光以除去凹部外部的多余金属并使装置平坦化。

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