公开(公告)号：WO2017160681A1

公开(公告)日：2017-09-21

申请号：PCT/US2017/022022

申请日：2017-03-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： CHONG, Yan ,  RAVEZZI, Luca ,  YEUNG, Alfred ,  PARTOVI, Hamid

IPC: G01R19/165

Abstract: A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.

Abstract translation: 自参考片上电压下降检测器从集成电路的配电网络的电源电压生成参考电压，并将该参考电压与瞬态电源电压进行比较以检测电压下降 。 由于位于管芯上，检测器以低等待时间响应于检测到的电压下降事件。 而且，通过从集成电路的电源域产生参考电压而不是使用单独的参考电压源，检测器不会引入与单独电源域相关的噪声和失真。

公开(公告)号：WO2017040239A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/048857

申请日：2016-08-26

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： THAIK, Rich ,  YEUNG, Alfred ,  LAMBERT, April ,  PLUNKETT, Jeremy

IPC: H01L23/522 ,  H01L23/50

CPC classification number: H03K5/1252 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/525

Abstract: A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.

Abstract translation: 在电路设计完成之后，半导体芯片允许选定数量的管芯上的去耦电容连接到大规模集成电路（VLSI）系统。 半导体芯片包括设置在封装基板上的集成电路，以及经由可编程连接阵列经由封装基板与集成电路电连接的配电网。

公开(公告)号：WO2017019052A1

公开(公告)日：2017-02-02

申请号：PCT/US2015/042592

申请日：2015-07-29

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： GOYAL, Ayush ,  MITCHELL, Phil

IPC: G06F13/14 ,  G06F1/04

CPC classification number: G06F1/04 ,  G06F11/0757 ,  G06F13/14

Abstract: Systems and methods for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.

Abstract translation: 基于与数据请求相关联的时钟计数器产生超时信号的系统和方法。 接口组件被配置为从主设备接收数据请求并将数据请求转发到从设备。 超时组件被配置用于在接收到与来自从设备的数据请求相关联的数据响应之前响应于确定与时钟计数器相关联的阈值电平来保持与数据请求相关联的时钟计数器并产生超时信号 。

公开(公告)号：WO2017019051A1

公开(公告)日：2017-02-02

申请号：PCT/US2015/042589

申请日：2015-07-29

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： DABIRI, Dariush ,  GUPTA, Tarun ,  NAGAPUDI, Venkatesh

IPC: H01B11/02 ,  H01B13/016

CPC classification number: H04B3/50

Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals.

Abstract translation: 电缆系统和组件集成了减少数量的双轴铜对，以传输速度大于或等于百兆字节每秒的全双工传输信号进行发送和接收。 双轴向铜对的数量减少包括四个或更少的双轴铜对，其中每对形成用于信号的无源或主动通信的单个双轴全双工电缆。

公开(公告)号：WO2017014752A1

公开(公告)日：2017-01-26

申请号：PCT/US2015/041322

申请日：2015-07-21

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： ASHCRAFT, Matthew ,  NELSON, Christopher

IPC: G06F9/30

CPC classification number: G06F9/30043

Abstract: Systems and methods are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low- level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.

Abstract translation: 提供了系统和方法，用于简化在精简指令集计算（RISC）中使用的负载获取和存储释放语义。 将语义转换为微操作或用于实现复杂机器指令的低级指令，可以避免执行复杂的新内存操作。 使用一个或多个数据存储器屏障操作结合加载和存储操作可以提供足够的顺序，因为数据存储器屏障确保在执行后续指令之前执行和完成先前的指令。

公开(公告)号：WO2017011021A1

公开(公告)日：2017-01-19

申请号：PCT/US2015/042791

申请日：2015-07-30

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： MITTAL, Millind

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/452 ,  G06F2212/602

Abstract: Facilitating reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

Abstract translation: 提供了片上系统（SoC）的多级高速缓存存储器架构中减少延迟的方法。 一种方法涉及通过设备包括多个多处理器中央处理单元核心的第一数据进入多个高速缓存存储器中的第一高速缓存存储器，多个高速缓存存储器与多级高速缓存存储器结构相关联。 该方法还包括产生控制信息，该控制信息包括：使得多个高速缓存存储器中的第二高速缓冲存储器的监视内容的第一指令，以确定是否为第二高速缓冲存储器满足定义的条件; 以及第二指令，用于基于满足所定义的条件的确定，将所述第一数据预取到所述多个高速缓冲存储器的第二高速缓冲存储器中。

公开(公告)号：WO2017003441A1

公开(公告)日：2017-01-05

申请号：PCT/US2015/038450

申请日：2015-06-30

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： CAGGIONI, Francesco ,  GIANNAKOPOULOS, Dimitrios

IPC: H04L7/00 ,  H04L29/06

CPC classification number: H04L7/041 ,  H04L2007/045

Abstract: Systems and methods for modifying a data stream for rate adaptation. A clock component receives a data stream at a first clock rate. In an aspect, a rate adaptation component inserts a first identification codeword into a particular location in the data stream based on a set of encoding rules in response to a determination that the first clock rate is lower than a second clock rate associated with a device configured for receiving a rate-adapted version of the data stream. In another aspect, the rate adaptation component removes a predefined codeword from the data stream and transforms another predefined codeword in the data stream into a second identification codeword in response to a determination that the first clock rate is greater than the second clock rate.

Abstract translation: 用于修改速率适配的数据流的系统和方法。 时钟分量以第一时钟速率接收数据流。 在一方面，速率适配组件响应于第一时钟速率低于与配置的设备相关联的第二时钟速率的确定，基于一组编码规则将第一标识码字插入数据流中的特定位置 用于接收数据流的速率适配版本。 在另一方面，响应于第一时钟速率大于第二时钟速率的确定，速率自适应组件从数据流中去除预定义的码字，并将数据流中的另一个预定码字变换为第二标识码字。

公开(公告)号：WO2016200411A1

公开(公告)日：2016-12-15

申请号：PCT/US2015/042798

申请日：2015-07-30

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： YEUNG, Alfred ,  COHAN, Ronen

IPC: H03K19/094

CPC classification number: H01L27/0248

Abstract: A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.

Abstract translation: 去耦电容电路设计有助于高工作频率，而不牺牲面积效率。 为了解决高操作频率和面积效率的有时相反的设计标准，p沟道场效应晶体管（PFET）和n沟道场效应晶体管以半交叉耦合（HCC）方式连接。 然后，HCC电路由至少一个区域有效电容（AEC）装置补充。 半交叉耦合晶体管满足高频设计要求，而AEC器件满足高区域效率要求。 该设计消除了一些常规DCAP设计中固有的工作频率和面积效率之间的不利权衡。

公开(公告)号：WO2016028452A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/042591

申请日：2015-07-29

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： DABIRI, Dariush

IPC: H03M13/03 ,  H03M1/12

CPC classification number: H03M13/2906 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/251 ,  H03M13/3746 ,  H03M13/616 ,  H03M13/6325 ,  H04L1/00 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057

Abstract: A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data based on an FEC code that has a symbol size that is not matched to a symbol size of a hexacode. Any code where the symbol size is less than the sample size for coding can be serially concatenated. During decoding the multi-level decoding leech lattice and FEC decoder can iteratively pass their outputs back and forth to each other until the encoded bits are decoded.

Abstract translation: 收发器架构可以包含用于传送高速传输的编码器和解码器。 编码器可以基于具有与六进制码的符号大小不匹配的符号大小的FEC码对信号数据进行调制。 符号大小小于编码的样本大小的任何代码都可以串行级联。 在解码期间，多级解码水蛭格和FEC解码器可以迭代地将它们的输出相互前后传递到彼此直到编码比特被解码。

公开(公告)号：WO2012027146A2

公开(公告)日：2012-03-01

申请号：PCT/US2011/047747

申请日：2011-08-15

Applicant: APPLIED MICRO CIRCUITS CORPORATION ,  GREENBERG, Reid ,  ZHOVNIROVSKY, Igor ,  ROY, Subhash

Inventor： GREENBERG, Reid ,  ZHOVNIROVSKY, Igor ,  ROY, Subhash

IPC: G02B6/38

CPC classification number: G02B6/4292 ,  G02B6/322 ,  G02B6/3853 ,  G02B6/4206

Abstract: A fiber optical connector microlens is provided with a self- aligning optical fiber cavity. The microlens includes a convex first lens surface and a second lens surface. A fiber alignment cavity is integrally formed with the second lens surface to accept an optical fiber core. A lens body is interposed between the first and second lens surfaces, having a cross-sectional area with a lens center axis, and the fiber alignment cavity is aligned with the lens center axis. In a first aspect, the fiber alignment cavity penetrates the lens second surface. In a second aspect, an integrally formed cradle with a cradle surface extends from the lens second surface, and a channel is formed in the cradle surface, with a center axis aligned with the lens center axis. The fiber alignment cavity includes a bridge covering a portion of the channel.

Abstract translation: 光纤连接器微透镜设置有自对准光纤腔。 微透镜包括凸起的第一透镜表面和第二透镜表面。 光纤对准空腔与第二透镜表面一体形成以接受光纤芯。 透镜体插入在第一和第二透镜表面之间，具有透镜中心轴线的横截面面积，并且光纤对准腔体与透镜中心轴线对准。 在第一方面，光纤对准腔穿透透镜第二表面。 在第二方面中，具有支架表面的整体形成的支架从透镜第二表面延伸，并且在支架表面中形成有与透镜中心轴对准的中心轴的通道。 光纤对准腔包括覆盖通道的一部分的桥。