公开(公告)号：WO2021155521A1

公开(公告)日：2021-08-12

申请号：PCT/CN2020/074385

申请日：2020-02-06

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： CAO, Kanyu ,  SHANG, Weibing

IPC: G11C7/06

Abstract: A sense amplifier circuit, memory device and related operation methods are provided. The sense amplifier circuit includes an amplification circuit for amplifying a voltage signal and a compensation circuit coupled to the amplification circuit. The amplification circuit includes a first inverting amplifier and a second inverting amplifier cross-coupled with each other, with the first inverting amplifier connected to a first bitline and the second inverting amplifier connected to a second bitline. The compensation circuit includes a first, a second, a third, and a fourth switch circuits, and is configured to generate a compensation voltage between the first bitline and the second bitline by conducting charge injections through operating the switch circuits to compensate an input-referred offset voltage of the amplification circuit. The operation methods take into consideration the effect of charge propagation on the bitlines to the voltages, therefore more accurately compensate the input-referred offset voltage.

公开(公告)号：WO2020098470A1

公开(公告)日：2020-05-22

申请号：PCT/CN2019/113589

申请日：2019-10-28

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： WU, Ping-Heng ,  HSU, Wen Hao

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprises an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device.

公开(公告)号：WO2020063721A1

公开(公告)日：2020-04-02

申请号：PCT/CN2019/108058

申请日：2019-09-26

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： PAN, Xiaodong

IPC: H01L21/66 ,  G01R31/00 ,  G01N21/88 ,  G06K9/46 ,  G06T7/00

Abstract: A wafer processing method and apparatus, a storage medium and an electronic device are disclosed, relating to the field of integrated circuit (IC) manufacturing and wafer stacking. The wafer processing method includes: partitioning a target wafer into one or more pre-divided areas each having one or more dies; determining area ratings for each pre-divided area based on test data of the dies in each pre-divided area; and feeding the area ratings of the pre-divided areas to a trained classification model to determine a classification category of the target wafer; identifying a second wafer having a same classification category as the target wafer; and stacking the target wafer with the second wafer. This method improves the production yield of stacked ICs.

公开(公告)号：WO2020048385A1

公开(公告)日：2020-03-12

申请号：PCT/CN2019/103420

申请日：2019-08-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： KE, Weibao

IPC: H01L21/66

Abstract: A semiconductor chip and a circuit and a method for electrically testing a semiconductor chip are disclosed, which pertain to the field of semiconductor technology. The semiconductor chip includes: a first electrical connection point, configured to connect a first pole of a force power supply in a Kelvin testing circuit; and a second electrical connection point, configured to connect a first terminal of a detecting device in the Kelvin testing circuit, wherein the first electrical connection point and the second electrical connection point are connected with each other within the semiconductor chip, and the first pole of the force power supply and the first terminal of the detecting device are arranged on the same side of the Kelvin testing circuit. According to the present disclosure, the semiconductor chip can be electrically tested with an enhanced accuracy and no impact from external contact and conduction resistances.

公开(公告)号：WO2020048381A1

公开(公告)日：2020-03-12

申请号：PCT/CN2019/103359

申请日：2019-08-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： HSU, Chia-Chi

IPC: G01R31/28

Abstract: A chip test device and a chip test method are provided. The chip test device may include a chip socket (300) and an interface card (200) comprising a signal synthesizer (210), a plurality of first interfaces and a second interface. The signal synthesizer may be configured to synthesize a plurality of low-frequency first signals output from a plurality of testers (100) into a high-frequency second signal and transmit the second signal to the chip socket (300). The plurality of first interfaces (220) may be arranged in a plurality of inputs of the signal synthesizer for connecting the testers (100), and the second interface (230) may be arranged in an output of the signal synthesizer (210) for connecting the chip socket (300). By synthesizing the low-frequency first signals into the high-frequency second signal, a high-frequency test may be conducted using a plurality of low-frequency testers (100).

公开(公告)号：WO2020001549A1

公开(公告)日：2020-01-02

申请号：PCT/CN2019/093319

申请日：2019-06-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： ZHOU, Bukang

IPC: H01L21/28 ,  H01L29/78

Abstract: A method for fabricating a transistor gate and a transistor structure thereof are disclosed herein. The method comprises: providing a substrate having a source region and a drain region; forming a gate oxide layer, a first polysilicon layer, a first isolation oxide layer, and a second polysilicon layer; doping the first polysilicon layer and second polysilicon layer to form a pre-gate structure; performing a annealing process so that the doped first polysilicon layer and second polysilicon layer are simultaneously and separately recrystallized to a first conductive silicon layer and a second conductive silicon layer, and electrically connecting the first conductive polysilicon layer and the second conductive polysilicon layer to each other; successively forming a conductive layer and a dielectric layer; forming a protective layer on a portion of the dielectric layer; etching from the dielectric layer until the gate oxide layer is exposed; and removing the protective layer to form the transistor gate.

公开(公告)号：WO2019129257A1

公开(公告)日：2019-07-04

申请号：PCT/CN2018/125298

申请日：2018-12-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： LIU, Chih Cheng

IPC: H01L23/525

CPC classification number: H01L23/5252

Abstract: An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.

公开(公告)号：WO2019085848A1

公开(公告)日：2019-05-09

申请号：PCT/CN2018/112327

申请日：2018-10-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： LIU, Chih Cheng

IPC: H01L27/108 ,  H01L21/8242

Abstract: A semiconductor layout structure for a dynamic random access memory (DRAM) array comprises a plurality of active areas, an isolation structure and a plurality of word lines in a semiconductor substrate, where the isolation structure is situated among the plurality of active areas. Each of the plurality of active areas comprises a first segment extending in a first direction and a second segment extending in a second direction, one end of the first segment connected to an end of the second segment such that the active area presents a "V" shape. Two of the plurality of word lines intersect and traverse the first and second segments in each of the active areas respectively.

公开(公告)号：WO2020108315A1

公开(公告)日：2020-06-04

申请号：PCT/CN2019/118465

申请日：2019-11-14

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： LIN, You-Hsien

IPC: H01L23/48 ,  H01L21/768 ,  H03K19/0175 ,  G01R31/28 ,  G01R31/317

Abstract: A signal transmission circuit and method for testing an integrated circuit (IC) are disclosed. The signal transmission circuit includes: an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal; a transfer chain, including multiple stages of serially-connected transfer circuits, where adjacent transfer circuits in the transfer chain are connected via a through silicon via (TSV), the transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal in stage by stage in response to the clock signal; and multiple signal output ends, where a first test signal input end of each stage of transfer circuit is correspondingly connected to one signal output end. The signal transmission circuit improves the effective utilization rate of a chip in an IC having a TSV test circuit.

公开(公告)号：WO2020103839A1

公开(公告)日：2020-05-28

申请号：PCT/CN2019/119527

申请日：2019-11-19

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： LU, Tianchen ,  GUO, Ruei-Yuan

IPC: G06F21/71

Abstract: The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.