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    OPTIMIZING POWER DELIVERY OF A POWER CONVERTER
    1.
    发明申请
    OPTIMIZING POWER DELIVERY OF A POWER CONVERTER 审中-公开

    公开(公告)号：WO2022026181A1

    公开(公告)日：2022-02-03

    申请号：PCT/US2021/041544

    申请日：2021-07-14

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. ,  MACKAY, Graeme G.

    Inventor： SHARMA, Ajit ,  LAWRENCE, Jason W.

    IPC: H02M3/156 ,  H02J7/00

    Abstract: A power delivery system may include a power converter configured to electrically couple to a power source and further configured to supply electrical energy to one or more loads electrically coupled to an output of the power converter and control circuitry comprising a feedback loop configured to monitor a voltage derived from the power source and control a limit for a current supplied from the power source to the one or more loads based on the voltage derived from the power source.

    ENCODING FOR MULTI-DEVICE SYNCHRONIZATION OF DEVICES
    2.
    发明申请
    ENCODING FOR MULTI-DEVICE SYNCHRONIZATION OF DEVICES 审中-公开
    编码器件的多器件同步

    公开(公告)号：WO2018071147A1

    公开(公告)日：2018-04-19

    申请号：PCT/US2017/052484

    申请日：2017-09-20

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. ,  MACKAY, Graeme Gordon

    Inventor： MACKAY, Graeme Gordon ,  MAY, Jeffrey Allen ,  BIAN, Jieren

    IPC: H04L12/40 ,  H04L12/413

    Abstract: A distributed network system may include a shared communication bus that operates in accordance with a communication protocol and a plurality of devices coupled to the bus. In accordance with the communication protocol, when one or more of the plurality of devices is actively transmitting data on the bus, each of the plurality of devices receives data via the bus such that bidirectional communication is established among the plurality of devices via the bus, each of the plurality of devices monitors a bus state of the shared communication bus to avoid data contention and to synchronize receipt of encoded symbols and encoded messages comprising encoded symbols via the bus, and each actively transmitting device of the plurality of devices compares the bus state to a desired state of such actively transmitting device to determine a priority among actively transmitting devices of the plurality of devices with respect to the bus.

    Abstract translation: 分布式网络系统可以包括根据通信协议运行的共享通信总线和耦合到总线的多个设备。 根据通信协议，当多个设备中的一个或多个设备在总线上主动发送数据时，多个设备中的每一个都经由总线接收数据，使得经由总线在多个设备之间建立双向通信， 多个设备中的每一个设备监视共享通信总线的总线状态以避免数据争用并且经由总线同步接收编码符号和包括编码符号的编码消息，并且多个设备中的每个主动发送设备比较总线状态 到这种主动发送设备的期望状态，以确定多个设备中的主动发送设备相对于总线的优先级。

    DIGITAL SIGNAL ROUTING CIRCUIT
    3.
    发明申请
    DIGITAL SIGNAL ROUTING CIRCUIT 审中-公开
    数字信号路由电路

    公开(公告)号：WO2012164272A2

    公开(公告)日：2012-12-06

    申请号：PCT/GB2012/051193

    申请日：2012-05-25

    Applicant: WOLFSON MICROELECTRONICS PLC ,  MACKAY, Graeme ,  WIGNER, Jonathan ,  MCLEOD, Gordon

    Inventor： MACKAY, Graeme ,  WIGNER, Jonathan ,  MCLEOD, Gordon

    IPC: H04M1/60

    CPC classification number: H04M1/6025 ,  H04H60/04 ,  H04M1/72558

    Abstract: An integrated circuit is used for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8kHz or 16kHz can be processed concurrently with audio data at 44.1kHz or 48kHz.

    Abstract translation: 集成电路用于数字信号路由。 集成电路具有模拟和数字输入和输出，包括用于连接到其他集成电路的数字接口。 输入，包括数字接口，作为数据源。 输出，包括数字接口，充当数据目的地。 该集成电路还包括可用作数据源和数据目的地的信号处理块。 信号路由通过乘法累加块实现，该乘法块从一个或多个数据源获取数据，并且在任何所需的缩放之后生成数据目的地的输出数据。 来自数据源的数据在数据采样时钟的整个周期中被缓冲，使得乘法累加块可以在该周期中的任何点检索数据，并且乘法累加块的输出数据被缓冲在整个周期 数据采样时钟，使得数据目的地可以在该周期的任何时间点检索数据。 多个信号路径可以由用户或软件提供给设备的配置数据来定义。 乘法累加块以时分复用为基础进行操作，从而可以在采样时钟的一个周期内处理多个信号路径。 每个信号路径具有各自的采样时钟速率，并且具有不同采样时钟速率的路径可以彼此独立地以时分复用为基础通过乘法累加块路由。 因此，可以以44.1kHz或48kHz的音频数据同时处理8kHz或16kHz的语音信号。

    MAINTAINING OPERATION OF A POWER CONVERTER WITHIN A STABLE REGION OF A POWER CURVE OR THAT POWER CONVERTER
    4.
    发明申请
    MAINTAINING OPERATION OF A POWER CONVERTER WITHIN A STABLE REGION OF A POWER CURVE OR THAT POWER CONVERTER 审中-公开

    公开(公告)号：WO2022026182A1

    公开(公告)日：2022-02-03

    申请号：PCT/US2021/041547

    申请日：2021-07-14

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. ,  MACKAY, Graeme G.

    Inventor： SHARMA, Ajit ,  LAWRENCE, Jason W. ,  ZHANG, Lingli

    IPC: H02M3/156 ,  H02J7/00

    Abstract: A power delivery system (10) may include a power converter (20) configured to electrically couple to a power source (12) and further configured to supply electrical energy to one or more loads (18) electrically coupled to an output of the power converter and control circuitry configured to monitor a first voltage derived from the power source, wherein the first voltage is indicative of a total power demanded by the power converter, and control a limit for a current supplied from the power source to the one or more loads based on comparison of the first voltage to a threshold voltage, wherein the threshold voltage is indicative of a point within a range of operation of the power converter at which the power converter delivers a maximum amount of power to the one or more loads.

    CLAMPING CURRENT LIMIT OF A HYSTERETIC POWER CONVERTER TO A MINIMUM VALUE TO ENSURE GRACEFUL SHUTDOWN AT BATTERY END OF LIFE
    6.
    发明申请
    CLAMPING CURRENT LIMIT OF A HYSTERETIC POWER CONVERTER TO A MINIMUM VALUE TO ENSURE GRACEFUL SHUTDOWN AT BATTERY END OF LIFE 审中-公开

    公开(公告)号：WO2022026179A1

    公开(公告)日：2022-02-03

    申请号：PCT/US2021/041535

    申请日：2021-07-14

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. ,  MACKAY, Graeme G.

    Inventor： SHARMA, Ajit ,  LAWRENCE, Jason W. ,  KING, Eric J.

    IPC: H02M1/36 ,  H02M1/00

    Abstract: A system may include a power source, a power converter having an input coupled to the power source and an output for supplying electrical energy to a load, and a control circuit for controlling operation of the power converter. The control circuit may include a first feedback control subsystem configured to monitor an output voltage present at the output of the power converter and regulate the output voltage at or about a predetermined regulated voltage level in a normal mode of operation of the power converter and a second feedback control subsystem configured to monitor an input voltage present between the power source and the input of the power converter and responsive to the input voltage decreasing below a predetermined minimum voltage level, causing the power converter to operate in a protection mode of operation in order to maintain the input voltage at or about the predetermined minimum voltage level.

    RANDOMIZATION OF CURRENT IN A POWER CONVERTER
    9.
    发明申请
    RANDOMIZATION OF CURRENT IN A POWER CONVERTER 审中-公开

    公开(公告)号：WO2021236308A1

    公开(公告)日：2021-11-25

    申请号：PCT/US2021/029584

    申请日：2021-04-28

    Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. ,  MACKAY, Graeme G.

    Inventor： LAWRENCE, Jason W.

    IPC: H02M1/00 ,  H02M1/44 ,  H02M3/156 ,  H02M3/158

    Abstract: A method of randomizing inductor current in at least one of a plurality of parallel coupled peak/valley current-controlled power converters may include comparing the inductor current to a threshold to generate a comparison signal, delaying the comparison signal by a plurality of delay amounts to generate a plurality of delayed versions of the comparison signal, and randomly selecting one of the plurality of delayed versions of the comparison signal for controlling the inductor current during one or both of a charging state and a transfer state of the at least one of the plurality of parallel coupled peak/valley current-controlled power converters.

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