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    Active termination control method and system through module register
    5.
    发明专利
    Active termination control method and system through module register 有权
    主动终止控制方法和通过模块寄存器的系统

    公开(公告)号：JP2008103073A

    公开(公告)日：2008-05-01

    申请号：JP2007280300

    申请日：2007-10-29

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー,インコーポレイテッドMicron Technology, Inc.

    Inventor： JANZEN JEFFERY W

    IPC: G11C11/4093 ,  G06F3/00 ,  G06F12/00 ,  G06F13/40 ,  G11C11/401

    CPC classification number: G06F13/4086

    Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for an active termination control in a memory by a module register providing an active termination control signal to the memory. SOLUTION: The module register monitors a system command bus for read and write commands. In the case of detecting the read or write command, the module register generates the active termination control signal to the memory. The memory turns on the active termination based on information being programmed into one or more mode registers of the memory. The memory maintains the active termination in an ON state for a predetermined time based on the information being programmed into one or more mode registers of the memory. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于通过向存储器提供有效终止控制信号的模块寄存器来在存储器中进行主动终止控制的方法和装置。

    解决方案：模块寄存器监视系统命令总线以进行读写命令。 在检测到读或写命令的情况下，模块寄存器产生到存储器的有效终止控制信号。 存储器基于被编程到存储器的一个或多个模式寄存器中的信息来打开活动终止。 存储器基于正被编程到存储器的一个或多个模式寄存器中的信息将活动终止维持在ON状态达预定时间。 版权所有（C）2008，JPO＆INPIT

    Film composition deposited on substrate, and its semiconductor device
    6.
    发明专利
    Film composition deposited on substrate, and its semiconductor device 审中-公开
    基底上沉积的膜组合物及其半导体器件

    公开(公告)号：JP2008010888A

    公开(公告)日：2008-01-17

    申请号：JP2007235523

    申请日：2007-09-11

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー,インコーポレイテッドMicron Technology, Inc.

    Inventor： SANDHU GURTEJ ,  DERDERIAN GARO J

    IPC: C23C16/30 ,  H01L21/285 ,  C23C16/44 ,  H01L21/28 ,  H01L21/283 ,  H01L21/316 ,  H01L21/365 ,  H01L21/768 ,  H01L27/10 ,  H01L29/51

    CPC classification number: H01L21/76843 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28167 ,  H01L21/28562 ,  H01L21/31612 ,  H01L21/76868 ,  H01L29/51

    Abstract: PROBLEM TO BE SOLVED: To provide a film composition deposited on a substrate and its semiconductor device. SOLUTION: An initiation layer is formed by exposing a substrate to at least an adhesive material enough to be adsorbed by the material on the substrate. The initiation layer gives a first reactive region. The reactive region is made to chemically react with the first reactive material under an atomic layer deposition condition to form a second reactive region. The second reactive region is made to chemically react with a second reactive material under a process condition enough to form a reactive layer on the initiation layer. This process is repeated to form a continuous reactive layer on the initiation layer. The adhesive material comprising the initiation layer is used that does not deteriorate by atomic layer deposition method. The initiation layer forms a final film together with one or a plurality of reactive layers. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供沉积在基板上的膜组合物及其半导体器件。 解决方案：通过将衬底暴露于至少足以被衬底上的材料吸附的粘合剂材料而形成起始层。 起始层产生第一反应区。 使反应区域在原子层沉积条件下与第一反应性材料发生化学反应以形成第二反应区域。 使第二反应区域在足以在起始层上形成反应层的工艺条件下与第二反应性材料发生化学反应。 重复该过程以在起始层上形成连续的反应层。 使用包含起始层的粘合剂材料，其不会通过原子层沉积方法劣化。 起始层与一个或多个反应层一起形成最终的膜。 版权所有（C）2008，JPO＆INPIT

    Low-voltage data path and current sense amplifier
    7.
    发明专利
    Low-voltage data path and current sense amplifier 审中-公开
    低电压数据路径和电流检测放大器

    公开(公告)号：JP2007207344A

    公开(公告)日：2007-08-16

    申请号：JP2006024795

    申请日：2006-02-01

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー,インコーポレイテッドMicron Technology, Inc.

    Inventor： TOMISHIMA SHIGEKI

    IPC: G11C11/409 ,  G11C11/4096

    CPC classification number: G11C7/062 ,  G11C7/1048 ,  G11C2207/063

    Abstract: PROBLEM TO BE SOLVED: To provide a data path capable of precisely and consistently detecting readout data under a low-voltage operation condition. SOLUTION: The data path 300 includes a local input/output (LIO) line 316 and a global input/output (GIO) line 350. A source follower circuit 325 includes first and second NMOS 334A, 334B having drains connected to first and second signal lines 352A, 352B of the GIO and gates connected to first and second signal lines 318A, 318B of the LIO. A third NMOS includes a source connected to the sources of the first and second NMOS, a gate connected to a reference voltage supply part, and a drain connected to a drain of a fourth NMOS. The fourth NMOS includes a gate to which a selection signal is applied and a source connected to the ground. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够在低电压操作条件下精确且一致地检测读出数据的数据路径。 数据路径300包括本地输入/输出（LIO）线路316和全局输入/输出（GIO）线路350.源极跟随器电路325包括第一和第二NMOS 334A，334B，其具有连接到第一 和连接到LIO的第一和第二信号线318A，318B的GIO和门的第二信号线352A，352B。 第三NMOS包括连接到第一和第二NMOS的源极的源极，连接到参考电压供应部分的栅极以及连接到第四NMOS的漏极的漏极。 第四NMOS包括施加选择信号的栅极和连接到地的源极。 版权所有（C）2007，JPO＆INPIT

    Negative voltage driving of digit line insulation gate
    9.
    发明专利
    Negative voltage driving of digit line insulation gate 审中-公开
    数字线绝缘门的负电压驱动

    公开(公告)号：JP2006228261A

    公开(公告)日：2006-08-31

    申请号：JP2005037029

    申请日：2005-02-15

    Applicant: Micron Technology Inc ,  ミクロン テクノロジー,インコーポレイテッドMicron Technology,Inc.

    Inventor： TOMISHIMA SHIGEKI

    IPC: G11C11/409

    CPC classification number: G11C7/08 ,  G11C2207/005

    Abstract: PROBLEM TO BE SOLVED: To decrease a leakage current at the time of standby due to short circuit of a row and a column in a semiconductor memory chip. SOLUTION: In the case of a row of a memory pre-charged to negative word line voltage (VNWL), that is a word line, when a gate of an insulation (ISO) transistor connected to the short-circuited word line and digit line is held at the VNWL level by an insulation signal driven to the VNWL level during a standby state of the row of the memory, the leakage current at the time of standby passing through a P sense amplifier in the memory is almost prevented. Since the leakage current at the time of standby is decreased, whole consumption of a current Icc is decreased from supply voltage of operation voltage of a memory circuit, thereby, power consumption of the circuit at the time of standby is decreased. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了减少由于半导体存储器芯片中的行和列的短路而在待机时的漏电流。

    解决方案：在将预充电到负字线电压（VNWL）的行的一行作为字线的情况下，当连接到短路字线的绝缘（ISO）晶体管的栅极 并且数字线通过在存储器行的待机状态期间被驱动到VNWL电平的绝缘信号保持在VNWL电平，几乎防止通过存储器中的P读出放大器的待机时的漏电流。 由于在待机时的漏电流减小，所以电流Icc的整体消耗从存储电路的工作电压的电源电压下降，从而在待机时电路的功耗降低。 版权所有（C）2006，JPO＆NCIPI

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