中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

675 records (took 0.037 seconds)

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    1.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开
    3D半导体器件和结构

    公开(公告)号：WO2018071143A2

    公开(公告)日：2018-04-19

    申请号：PCT/US2017/052359

    申请日：2017-09-19

    Applicant: MONOLITHIC 3D INC.

    Inventor： OR-BACH, Zvi ,  HAN, Jin-Woo ,  CRONQUIST, Brian ,  LUSKY, Eli

    IPC: H01L27/06 ,  H01L21/8238 ,  H01L27/11551 ,  H01L27/108 ,  H01L27/11

    CPC classification number: H01L27/11551 ,  H01L27/1104

    Abstract: A 3D device, the device comprising: a first stratum comprising a first bit-cell array, the first bit-cell array includes three independent first rows; a second stratum including a second bit-cell array, the second bitcell array includes three independent second rows, where the second stratum overlays the first stratum; and at least three vertical bitlines each connected to respective three horizontal first bitlines and three horizontal second bitlines, where the three horizontal first bitlines include control of the first bit-cell array, where the three horizontal second bitlines include control of the second bit-cell array, and where each of the three vertical bitlines could be used to control a different one of the three independent first rows, or control a different one of the three independent second rows

    Abstract translation: 一种3D器件，所述器件包括：第一层，其包括第一位单元阵列，所述第一位单元阵列包括三个独立的第一行; 包括第二位单元阵列的第二层，所述第二位单元阵列包括三个独立的第二行，其中所述第二层覆盖所述第一层; 以及至少三条垂直位线，每条垂直位线分别连接到相应的三条水平第一位线和三条水平第二位线，其中三条水平第一位线包括对第一位单元阵列的控制，其中三条水平第二位线包括对第二位单元 阵列，并且其中三个垂直位线中的每一个可以用于控制三个独立的第一行中的不同的一个，或者控制三个独立的第二行中的不同的一个

    A 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH HEAT SPREADER
    3.
    发明申请
    A 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH HEAT SPREADER 审中-公开

    公开(公告)号：WO2023049132A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/044165

    申请日：2022-09-21

    Applicant: MONOLITHIC 3D INC.

    Inventor： OR-BACH, Zvi ,  HAN, Jin-Woo ,  CRONQUIST, Brian

    IPC: H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H01L23/528 ,  H01L23/367 ,  H04L25/02 ,  H04L27/26 ,  G06N3/08

    Abstract: A semiconductor device, the device including: a first level including a plurality of first transistors, where at least one of the plurality of first transistors includes a single crystal channel; a first interconnect layer disposed on top of the plurality of first transistors; a plurality of ground lines disposed underneath the plurality of first transistors, the plurality of ground lines connecting from a ground to at least one of the plurality of first transistors; a plurality of power lines disposed underneath the plurality of first transistors, the plurality of power lines connecting from power to at least one of the plurality of first transistors; and a heat conductive material disposed so to be in contact with the plurality of ground lines and the plurality of power lines, where the heat conductive material includes diamond molecules.

    SEMICONDUCTOR DEVICE AND STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

    公开(公告)号：WO2012015550A3

    公开(公告)日：2012-02-02

    申请号：PCT/US2011/042071

    申请日：2011-06-28

    Applicant: MONOLITHIC 3D, INC. ,  OR-BACH, Zvi ,  SEKAR, Deepak C. ,  CRONQUIST, Brian ,  WURMAN, Zeev

    Inventor： OR-BACH, Zvi ,  SEKAR, Deepak C. ,  CRONQUIST, Brian ,  WURMAN, Zeev

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

    Abstract: A method for fabrication of semiconductor device comprising a first wafer comprising first single crystal layer comprising first transistors, first alignment marks, and first transistors interconnect layers comprising at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum; and comprising a step of implant and high temperature activation to form a conductive layer within a second wafer; and forming a second crystallized layer on top of said first wafer by transferring said conductive layer using ion-cut process, and forming second transistors on said second crystallized layer wherein said second transistors source and drain comprises portion of said first conductive layer.

    SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE
    5.
    发明专利
    SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE 未知

    公开(公告)号：SG10201805793VA

    公开(公告)日：2018-08-30

    申请号：SG10201805793V

    申请日：2010-10-08

    Applicant: MONOLITHIC 3D INC ,  OR BACH ZVI

    Inventor： OR-BACH ZVI ,  CRONQUIST BRIAN ,  BEINGLASS ISRAEL ,  DE JONG J ,  SEKAR DEEPAK ,  WURMAN ZEEV

    Abstract: SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. Fig.A -325-

    SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE
    6.
    发明专利
    SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE 未知

    公开(公告)号：SG10201406527RA

    公开(公告)日：2014-12-30

    申请号：SG10201406527R

    申请日：2010-10-08

    Applicant: MONOLITHIC 3D INC ,  OR BACH ZVI

    Inventor： OR-BACH ZVI ,  CRONQUIST BRIAN ,  BEINGLASS ISRAEL ,  DE JONG J L ,  SEKAR DEEPAK C ,  WURMAN ZEEV

    Abstract: SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. Fig. 3A

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    7.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

    公开(公告)号：WO2018071143A3

    公开(公告)日：2018-04-19

    申请号：PCT/US2017/052359

    申请日：2017-09-19

    Applicant: MONOLITHIC 3D INC.

    Inventor： OR-BACH, Zvi ,  HAN, Jin-Woo ,  CRONQUIST, Brian ,  LUSKY, Eli

    IPC: H01L27/06 ,  H01L21/8238 ,  H01L27/11551 ,  H01L27/108 ,  H01L27/11

    Abstract: A 3D device, the device comprising: a first stratum comprising a first bit-cell array, the first bit-cell array includes three independent first rows; a second stratum including a second bit-cell array, the second bitcell array includes three independent second rows, where the second stratum overlays the first stratum; and at least three vertical bitlines each connected to respective three horizontal first bitlines and three horizontal second bitlines, where the three horizontal first bitlines include control of the first bit-cell array, where the three horizontal second bitlines include control of the second bit-cell array, and where each of the three vertical bitlines could be used to control a different one of the three independent first rows, or control a different one of the three independent second rows

    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS
    10.
    发明申请
    3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS 审中-公开

    公开(公告)号：WO2019060798A1

    公开(公告)日：2019-03-28

    申请号：PCT/US2018/052332

    申请日：2018-09-23

    Applicant: MONOLITHIC 3D INC.

    Inventor： OR-BACH, Zvi ,  HAN, Jin-Woo ,  CRONQUIST, Brian ,  LUSKY, Eli

    IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

    Abstract: A first and a second 3D device, both devices including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. optical waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, where the second level overlays the first level, the third level overlays the second level, and the fourth level overlays the third level, where the first level includes a substrate included of single crystal silicon, where the first device is much larger in surface area than the second device, and where the fourth level of the second device is very similar to a portion of the fourth level of the first device.

Patent Agency Ranking