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公开(公告)号：JP2010056503A
公开(公告)日：2010-03-11
申请号：JP2008264275
申请日：2008-10-10
Inventor： HSU YU PIN , CHANG YUAN MING , LEE WEI HENG , WU CHENG DA
IPC: H01L21/265 , H01J37/317
CPC classification number: H01L21/67253
Abstract: PROBLEM TO BE SOLVED: To provide a method for determining the performance of an injecting device, with use of a recycled wafer by measuring a sheet resistance of a dummy wafer by a four-point probe method in order to monitor the performance of the injecting device.
SOLUTION: A dopant barrier layer 14 is formed on a substrate (dummy wafer) 12, and a target layer (polysilicon layer) 16 is formed on the dopant barrier layer, and an injection is performed by the injecting device 20, and a sheet resistance of the polysilicon layer is measured by a four-point probe 22. Consequently, the naked substrate doesn't need polishing and is free of the reduction of thickness because being not scratched by the probe. The substrate can be repeatedly used endlessly when recycled by removing the dopant barrier layer and the polysilicon layer.
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：为了提供一种用于确定注射装置的性能的方法，使用再循环的晶片，通过四点探针法测量虚拟晶片的薄层电阻，以便监测其性能 注射装置。 解决方案：在衬底（虚拟晶片）12上形成掺杂剂阻挡层14，在掺杂剂阻挡层上形成目标层（多晶硅层）16，由注入装置20进行注入， 通过四点探头22测量多晶硅层的薄层电阻。因此，裸基板不需要抛光，并且由于没有被探针划伤而没有厚度的减小。 通过去除掺杂剂阻挡层和多晶硅层，可以循环地重复使用衬底。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2008053705A
公开(公告)日：2008-03-06
申请号：JP2007202260
申请日：2007-08-02
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L27/105 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L21/76897 , H01L27/0207 , H01L27/1052 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor memory in which an extending conductive plug is formed on each of opposite sides of its active region. SOLUTION: The method for manufacturing the semiconductor memory include steps: for forming a plurality of stripe blocks in dielectric structure of a substrate and then forming first etching mask which exposes the sidewall of the stripe blocks locally; for removing the stripe blocks locally by using the first etching mask and forming second etching mask by cutting down the width of the stripe blocks; and for forming a plurality of apertures in the dielectric structure by removing the portions of dielectric structure not covered by the second etching mask, and then forming the conducting plug in the aperture. The plurality of the apertures have a plurality of first apertures disposed between first blocks and a plurality of second apertures disposed between second blocks. The first apertures and the second apertures project from the opposite sides of the active region, respectively. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：提供一种半导体存储器的制造方法，其中在其有源区域的相对侧的每一侧上形成有延伸的导电插塞。 解决方案：用于制造半导体存储器的方法包括以下步骤：用于在衬底的介电结构中形成多个条状块，然后形成局部暴露条纹块的侧壁的第一蚀刻掩模; 用于通过使用第一蚀刻掩模局部去除条纹块并通过减小条形块的宽度来形成第二蚀刻掩模; 并且通过去除未被第二蚀刻掩模覆盖的介质结构的部分，然后在孔中形成导电插塞，以在电介质结构中形成多个孔。 多个孔具有设置在第一块之间的多个第一孔和设置在第二块之间的多个第二孔。 第一孔和第二孔分别从活性区的相对侧突出。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2004063901A
公开(公告)日：2004-02-26
申请号：JP2002221915
申请日：2002-07-30
Inventor： WANG TING-SHING
IPC: H01L27/108 , H01L21/8242
Abstract: PROBLEM TO BE SOLVED: To avoid problems derived from a high aspect ratio encountered in a conventional hole by providing a fabrication process of a trench capacitor.
SOLUTION: First electrode plate of a memory cell is disposed on the circumferential edge at the lower surface part of an insular semiconductor structure in a substrate, a second electrode plate is disposed in the surface at the lower surface part of the insular semiconductor structure and in the surface of the substrate on the outside of the insular semiconductor structure, and a capacitor dielectric layer 112 is interposed between the second electrode plate and the first electrode plate. Furthermore, a transistor for controlling the trench capacitor C is disposed on the island-like semiconductor structure and that transistor is provided with a first source/drain 123, a second source/drain 124 and a gate electrode G. Furthermore, an embedded strap 126 is interposed between the second source/drain and the first electrode plate, and a conductive plug 134 is interposed between the first source/drain and a bit line B.
COPYRIGHT: (C)2004,JPO-
4.发明专利Phase shift mask and manufacturing method, and method for manufacturing semiconductor element 审中-公开相移屏蔽和制造方法及制造半导体元件的方法
公开(公告)号：JP2007183491A
公开(公告)日：2007-07-19
申请号：JP2006002630
申请日：2006-01-10
Inventor： LAI YEE-KAI
IPC: G03F1/34 , G03F1/68 , H01L21/027
Abstract: PROBLEM TO BE SOLVED: To provide a phase shift mask, a method for manufacturing the same, and a method for manufacturing a semiconductor element.
SOLUTION: The phase shift mask has a substrate and a plurality of phase shift patterns formed on the substrate. The method for manufacturing the phase shift mask includes the steps of: forming a polymer layer on the substrate; changing the molecular structure in a plurality of prescribed areas in the polymer; and removing the polymer layer except the prescribed areas. The method for manufacturing the semiconductor element using this phase shift mask includes the steps of: forming a photoresist layer on the substrate; exposing the photoresist layer to light with the use of the phase shift mask; and developing the photoresist layer.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 解决的问题：提供一种相移掩模，其制造方法以及半导体元件的制造方法。 解决方案：相移掩模具有衬底和形成在衬底上的多个相移图案。 制造相移掩模的方法包括以下步骤：在基底上形成聚合物层; 改变聚合物中多个规定区域中的分子结构; 除去规定区域以外的聚合物层。 使用该相移掩模制造半导体元件的方法包括以下步骤：在基板上形成光致抗蚀剂层; 使用相移掩模将光致抗蚀剂层曝光; 并显影光致抗蚀剂层。 版权所有（C）2007，JPO＆INPIT
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5.发明专利Semiconductor element with laminate structure, and method of manufacturing the same 有权具有层压结构的半导体元件及其制造方法
公开(公告)号：JP2009188400A
公开(公告)日：2009-08-20
申请号：JP2009014261
申请日：2009-01-26
Inventor： CHEN MIN LIANG , ZHAO HAI JUN
IPC: H01L21/02 , H01L21/3205 , H01L21/768 , H01L23/52
CPC classification number: H01L21/8221 , H01L23/481 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L27/105 , H01L27/108 , H01L2224/0401 , H01L2224/05554 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/13099 , H01L2224/1403 , H01L2224/16 , H01L2224/81894 , H01L2224/83856 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2224/05552 , H01L2224/80001
Abstract: PROBLEM TO BE SOLVED: To provide a method of laminating a plurality of semiconductor wafers, more specifically, without requiring cost in the field of integration of semiconductor elements. SOLUTION: The method of laminating wafers includes steps of: supplying a first wafer having a first metal connection layer; forming a first protective layer on the first metal connection layer; forming a first coupling pad within the first protective layer to form a first coupling pad layer; supplying a second wafer having a second metal connection layer; forming a second protective layer on the second metal connection layer; forming a second coupling pad within the second protective layer to form a second coupling pad layer; forming a first conductive junction layer on the first coupling pad layer and/or forming a second conductive junction layer on the second coupling pad layer; and laminating the second wafer on the first wafer by coupling the first coupling pad layer and a surface of the second coupling pad layer, which in turn corresponds to the first coupling pad layer, through at least one of the first conductive junction layer and the second conductive junction layer. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供一种层叠多个半导体晶片的方法，更具体地，不需要在半导体元件的集成领域中的成本。 解决方案：层压晶片的方法包括以下步骤：提供具有第一金属连接层的第一晶片; 在所述第一金属连接层上形成第一保护层; 在所述第一保护层内形成第一耦合焊盘以形成第一耦合焊盘层; 提供具有第二金属连接层的第二晶片; 在所述第二金属连接层上形成第二保护层; 在所述第二保护层内形成第二耦合焊盘以形成第二耦合焊盘层; 在所述第一耦合焊盘层上形成第一导电结层和/或在所述第二耦合焊盘层上形成第二导电结层; 以及通过将所述第一耦合焊盘层和所述第二耦合焊盘层的表面（其又对应于所述第一耦合焊盘层）通过所述第一导电结层和所述第二焊盘层中的至少一个耦合来将所述第二晶片层压在所述第一晶片上 导电结层。 版权所有（C）2009，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2007027738A
公开(公告)日：2007-02-01
申请号：JP2006192047
申请日：2006-07-12
Inventor： SHU SHIBUN , CHU CHIH-HSUN
IPC: H01L29/78
CPC classification number: H01L29/0653 , H01L29/6656 , H01L29/66628 , H01L29/66636
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce a short channel effect and to provide its manufacturing method.
SOLUTION: The semiconductor device comprises a substrate, a gate structure, a source region, a drain region, and two dielectric barrier layers. The gate structure is formed on the substrate. The source region and the drain region are formed on the substrate where the gate structure is formed, and the channel region is formed between the source region and the drain region under the gate structure. Two dielectric barrier layers are formed on the substrate under the gate structure between the source region and the drain region respectively. The dielectric barrier layers are used to reduce drain caused by DIBL effect in a nanometer scale device.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 解决的问题：提供一种能够减小短路效应并提供其制造方法的半导体装置。 解决方案：半导体器件包括衬底，栅极结构，源极区，漏极区和两个电介质阻挡层。 栅极结构形成在基板上。 在栅极结构形成的基板上形成源极区域和漏极区域，在栅极结构的栅极区域与漏极区域之间形成沟道区域。 分别在源极区域和漏极区域之间的栅极结构下的衬底上形成两个电介质阻挡层。 电介质阻挡层用于在纳米级装置中减少由DIBL效应引起的漏极。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2004047525A
公开(公告)日：2004-02-12
申请号：JP2002199565
申请日：2002-07-09
Inventor： SHIN-TAN PON , YUN-CHIN WAN , TON-CHUN YAN
IPC: H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115
Abstract: PROBLEM TO BE SOLVED: To provide a novel and effective method of boring contact holes.
SOLUTION: The method for boring a contact hole comprises a step for preparing a substrate provided sequentially, on the surface thereof, with first through fourth adjacent gate conducting structures with the second and third gate conducting structures located in an active region; a step for adaptively forming a wiring metal layer on the surface of the substrate in the surface part between the second and third gate conduction structures; a step for forming an inner layer dielectric layer having a planarized surface on the entire surface of the substrate, such that the wiring metal layer is covered and the gap between the first and second conduction structures and the gap between the third and fourth conducting structures are filled; and a step for boring a bit line contact hole in the inner layer dielectric layer, to expose the surface of the wiring metal layer.
COPYRIGHT: (C)2004,JPO-
8.发明专利Method for forming silicon nitride layer on gate oxide film of semiconductor device and annealing the nitride layer 有权在半导体器件的栅极氧化膜上形成氮化硅层并在硝酸盐层上退火的方法
公开(公告)号：JP2009272594A
公开(公告)日：2009-11-19
申请号：JP2008169521
申请日：2008-06-27
Inventor： WU CHENG-TA , CHUANG DA-YU , CHEN YEN-DA , LIN LIHAN
IPC: H01L29/78 , H01L21/318
CPC classification number: H01L21/28202 , H01L21/28185
Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a silicon nitride film on a gate oxide film, wherein the method solves at least one of the problems in prior arts. SOLUTION: The method for forming a silicon nitride film on a gate oxide film as a part of forming a gate structure in semiconductor devices includes a step of forming a layer of silicon nitride on the upper part of a gate oxide film of a semiconductor substrate by a nitriding treatment process, a step of heating the semiconductor substrate in an annealing chamber, a step of exposing the semiconductor substrate to N 2 in the annealing chamber, and a step of exposing the semiconductor substrate to a mixture of N 2 and N 2 O in the annealing chamber. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 解决的问题：提供一种在栅极氧化膜上形成氮化硅膜的方法，其中该方法解决现有技术中的至少一个问题。 解决方案：作为在半导体器件中形成栅极结构的一部分的在栅极氧化膜上形成氮化硅膜的方法包括在栅极氧化膜的上部形成氮化硅层的步骤 通过氮化处理工艺的半导体衬底，在退火室中加热半导体衬底的步骤，在退火室中将半导体衬底暴露于N
2 的步骤，以及将半导体衬底 在退火室中与N2 和N 2 O的混合物。 版权所有（C）2010，JPO＆INPIT -
9.发明专利Memory having charge storage node having at least a part positioned in trench of semiconductor substrate and electrically coupled with source/drain regions formed on substrate 审中-公开具有充电存储节点的存储器至少具有位于半导体衬底的部分并与衬底上形成的源/漏区电耦合的部件
公开(公告)号：JP2006279006A
公开(公告)日：2006-10-12
申请号：JP2005163077
申请日：2005-06-02
IPC: H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC classification number: H01L27/1087 , H01L27/10867
Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit facilitating manufacture by a new technology of a memory with a storage electrode formed in a downsized trench.
SOLUTION: Blocking features for a plurality of trenches 124 in a memory array is patterned by using a mask forming a plurality of straight strips passing through each memory array in a line writing direction. The charge storage node has a projection 120.3 on a first side of a trench adjacent to source/drain regions, and also has an upper surface portion (T) adjacent to the projection along the side face. A trench sidewall covers an upper surface (T), and has a part (S) that is roughly straight in a second side 124.2. A dielectric film 144.1 in the trench sidewall has a thicker part in the second side than that in the first side.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：提供一种集成电路，便于利用存储电极的新技术进行制造，该存储电极形成在小型化的沟槽中。 解决方案：通过使用形成沿线写入方向穿过每个存储器阵列的多个直条的掩模来对存储器阵列中的多个沟槽124的阻挡特征进行构图。 电荷存储节点在与源极/漏极区相邻的沟槽的第一侧上具有突起120.3，并且还具有与侧面相邻的突起的上表面部分（T）。 沟槽侧壁覆盖上表面（T），并且具有在第二侧124.2中大致直线的部分（S）。 沟槽侧壁中的电介质膜144.1在第二侧具有比第一侧更厚的部分。 版权所有（C）2007，JPO＆INPIT
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10.发明专利Correcting method of lithographic processing and forming method of overlapping mark 审中-公开图像处理的校正方法和重写标记的形成方法
公开(公告)号：JP2005268745A
公开(公告)日：2005-09-29
申请号：JP2004286935
申请日：2004-09-30
Inventor： CHEN TAI-YUAN
IPC: H01L21/027 , G03F7/00 , G03F7/20 , H01L21/203 , H01L21/44 , H01L21/66 , H01L23/544
CPC classification number: H01L22/20 , G03F7/70633 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a method of correcting lithographic processing when forming an overlapping mark. SOLUTION: Physical vapor depositing (PVD) is performed as if film were laminated on a wafer. Unsymmetrical deposition of the film on a side wall of opening portion relates to a variation of consumption of a target in the PVD treatment. Therefore, a location shift in the overlapping mark varies in each time duration. A formula relating to the consumption of the target and the location shift is extracted, and the formula is recorded on a controller system. A compensation value is obtained from the controller system, and it feeds back to next lithographic processing. Namely, error in a measurement of the overlapping mark can be reduced because the compensation value is fed back through the controller system so that the location shift in the overlapping mark brought from the consumption of the target in the PVD treatment may be corrected. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种在形成重叠标记时校正光刻处理的方法。
解决方案：物理气相沉积（PVD）被执行，就好像薄膜层压在晶片上一样。 膜在开口部侧壁上的不对称沉积与PVD处理中的靶的消耗变化有关。 因此，重叠标记中的位置偏移在每个持续时间内变化。 提取与目标消费和位置偏移有关的公式，公式记录在控制器系统上。 从控制器系统获得补偿值，并将其反馈到下一个平版印刷处理。 即，由于通过控制器系统反馈补偿值，可以减少重叠标记的测量误差，从而可以校正由PVD处理中的目标消耗引起的重叠标记中的位置偏移。 版权所有（C）2005，JPO＆NCIPI
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