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    Asynchronous reading cache memory and device controlling access to data memory with same cache memory
    5.
    发明专利
    Asynchronous reading cache memory and device controlling access to data memory with same cache memory 审中-公开
    异步读取高速缓存存储器和设备控制访问具有相同缓存存储器的数据存储器

    公开(公告)号：JP2005071380A

    公开(公告)日：2005-03-17

    申请号：JP2004248342

    申请日：2004-08-27

    Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： PISTOULET PIERRE

    IPC: G06F12/08 ,  G06F12/12 ,  G06F12/14 ,  G06F21/02

    CPC classification number: G06F12/1425 ,  G06F12/0875 ,  Y02D10/13

    Abstract: PROBLEM TO BE SOLVED: To provide an access controller with a simple structure allowing reduction of peak power consumption. SOLUTION: This access controller controlling access to a data memory has: a means storing a plurality of attributes (ATi) for defining a right of the access to the data memory (DMEM); cache memories (CMEM, CMC) storing a prescribed number of attributes; and a synchronous attribute retrieval circuit (ASC2) retrieving the attribute inside the storage means (DMEM, ATMEM) when the attribute is absent inside the cache memory. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有简单结构的访问控制器，从而降低峰值功耗。 控制对数据存储器的访问的该访问控制器具有：存储用于定义访问数据存储器（DMEM）的权限的多个属性（ATi）的装置; 存储规定数量属性的缓存存储器（CMEM，CMC）; 以及当高速缓冲存储器内部不存在属性时，在存储装置（DMEM，ATMEM）内检索属性的同步属性检索电路（ASC2）。 版权所有（C）2005，JPO＆NCIPI

    Process for automatic correction of spectral inversion in demodulator and device to implement the process
    7.
    发明专利
    Process for automatic correction of spectral inversion in demodulator and device to implement the process 有权
    用于自动校正分散器中的光谱反转的过程和实现该过程的装置

    公开(公告)号：JP2007020169A

    公开(公告)日：2007-01-25

    申请号：JP2006183340

    申请日：2006-07-03

    Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： MEYER JACQUES

    IPC: H04L27/22

    CPC classification number: H04L27/2273 ,  H03D3/00 ,  H04L27/22

    Abstract: PROBLEM TO BE SOLVED: To provide a technology capable of momentarily detecting a spectral inversion from a received signal in a pseudo way.
    SOLUTION: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type π/2 BPSK or MDP2. The process includes a step of demodulating the training sequence; steps (21, 22, 23) of calculating the differential correlation on a set of N received samples (R
    n ) and presumably sent samples (S
    n ) to generate a result; and a step of using the result to detect the beginning of the screen and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. The process can realize automatic process of the spectral inversion by the receiver.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种能够以伪方式从接收信号瞬时检测频谱反演的技术。 解决方案：数字通信系统中的接收机的频谱反演的校正过程：该过程允许在接收机中接收根据类型π/ 2 BPSK或MDP2可能已知的训练序列。 该过程包括解调训练序列的步骤; 计算一组N个接收样本（R SB> n ）和推测发送的样本（S n ）之间的差分相关性以产生结果的步骤（21,22,23） ; 以及在开始对帧的开始的检测之前，使用结果来检测屏幕的开始并且在上述接收器的接收链中订购频谱反转的步骤。 该过程可以实现接收机的频谱反演的自动处理。 版权所有（C）2007，JPO＆INPIT

    Decoding and error correction method
    8.
    发明专利
    Decoding and error correction method 有权

    公开(公告)号：JP2005512382A

    公开(公告)日：2005-04-28

    申请号：JP2003550369

    申请日：2002-11-29

    Applicant: エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： ユベルト デグワラ ,  ルワ パルリエ

    IPC: G06F11/10 ,  H03M13/37

    CPC classification number: H03M13/37

    Abstract: 本発明は、誤り訂正ステップと、復号化関数（Ａ
    −１ ）を使用した復号化ステップとからなる、初期の保護された符号ワード（Ｘ２）に対して誤りを有する可能性のある保護された符号ワード（Ｘ３）に適用可能な復号および誤り訂正方法に関する。 本発明によると、復号化ステップは、誤り訂正ステップの前に実行され、復号化関数（Ａ
    −１ ）を保護された符号ワード（Ｘ３）に適用して、
    符号化された誤り（Ｅ＊Ａ
    −１ ）を有する保護された復号化ワード（Ｘ４'）を得る。 長所：復号および誤り訂正時間の短縮。

    Dimming detection mosfet, and manufacturing method thereof
    9.
    发明专利
    Dimming detection mosfet, and manufacturing method thereof 审中-公开
    调光检测MOSFET及其制造方法

    公开(公告)号：JP2009044127A

    公开(公告)日：2009-02-26

    申请号：JP2008120484

    申请日：2008-05-02

    Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： ABELE NICOLAS

    IPC: H01L31/10 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L31/1136 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To form a structure of a component for attaining function of a photo-sensor and a dimmer while saving its space.
    SOLUTION: A light control detection MOSFET has two source and drain regions separated with a channel 130 extending along a first direction, and a substrate 100 irradiated with light and a gate conductive beam 140 extending along a second direction which is almost perpendicular to the first direction. On at least one supporting region, the beam is fixed at each of two edge portions and located on the channel region 130. The gate beam is almost opaque and flexible so that progressive modulation is applied to light reaching the channel 130 based on a curve which is controlled by a voltage difference between a gate voltage and bulk voltage wherein the voltage difference acts so as to bend the beam to come closer to the channel surface.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：为了形成用于获得光传感器和调光器的功能的部件的结构，同时节省空间。 光控制检测MOSFET具有沿着第一方向延伸的通道130和由光照射的基板100和沿第二方向延伸的栅极导电梁140分开的两个源极和漏极区域，第二方向几乎垂直于 第一个方向。 在至少一个支撑区域上，光束固定在两个边缘部分中的每一个并且位于通道区域130上。栅极光束几乎是不透明和柔性的，使得逐渐调制被施加到基于如下曲线的到达通道130的光 由栅极电压和体电压之间的电压差控制，其中电压差用于使光束弯曲成靠近通道表面。 版权所有（C）2009，JPO＆INPIT

    Whole processing device for data
    10.
    发明专利
    Whole processing device for data 审中-公开
    全数据处理设备

    公开(公告)号：JP2004206721A

    公开(公告)日：2004-07-22

    申请号：JP2003425525

    申请日：2003-12-22

    Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

    Inventor： LEHONGRE DENIS

    IPC: G06F7/02 ,  G06F7/22 ,  G11B20/14 ,  H03H17/02 ,  H03M5/00 ,  H03M5/04 ,  H03M5/14 ,  H03M7/46

    CPC classification number: G06F7/22 ,  G11B20/1426 ,  H03H17/0263 ,  H03M5/00 ,  H03M5/04 ,  H03M5/145 ,  H03M7/46

    Abstract: PROBLEM TO BE SOLVED: To reduce an operation time in the case of processing a large number of data.
    SOLUTION: This device is a digital data processor, more specifically, a device for reading the maximum value or the minimum value of data belonging to a set of 2
    n codes, an order relation is established and each code has a rank R constituted of 0 to 2
    n -1, respectively in the set. The device is a conversion circuit for each piece of digital data processed for generating the conversion of binary digits constituted of 2
    n binary elements T[x] having X=1 to 2
    n -1, T[2
    n -1]T[2
    n -2] T[x] to T[2] T[1] and is provided with the one in which T(x)=0 when X is absolutely larger than R and T(x)=1 when X is smaller than or equal to R here. The circuit for executing digital processing receives the result of this conversion.
    COPYRIGHT: (C)2004,JPO&NCIPI

    Abstract translation: 要解决的问题：在处理大量数据的情况下减少操作时间。 解决方案：该设备是数字数据处理器，更具体地，用于读取属于一组2 n 代码的数据的最大值或最小值的设备，建立了顺序关系 并且每个代码分别具有由0到2 n -1构成的秩R。 该装置是用于产生由具有X = 1至2 n n 个二进制元素T [x]构成的二进制数字的转换的每个数字数据的转换电路。 > -1，T [2 n -1] T [2 n -2] T [x]到T [2] T [1] 当X小于或等于R时，当X绝对大于R且T（x）= 1时，T（x）= 0。 用于执行数字处理的电路接收该转换的结果。 版权所有（C）2004，JPO＆NCIPI

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