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    WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS
    3.
    发明专利
    WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS 未知

    公开(公告)号：SG156550A1

    公开(公告)日：2009-11-26

    申请号：SG2008034795

    申请日：2008-05-06

    Applicant: VISWANADAM GAUTHAM

    Inventor： VISWANADAM GAUTHAM

    Abstract: A method and apparatus for manufacturing an integrated circuit (IC) device 90 is disclosed. A wafer 10 is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro- structures 16 that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface 12 of the wafer. The wafer with pre- formed conductive interconnect microstructures 16 are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side 12 devices are fabricated, the silicon material 20 is then removed from a second side 14 of the device wafer 10, opposite the first side, to expose the high temperature conductive interconnect microstructures 16. Contacts are formed on the second side of the device wafer using conductive metal. These contacts are electrically connected to the interior of the microstructures and thereby electrically connect with the functional device 26. The dies 90(1),90(2) are separated along the separation zones 88 between the dies to produce individualized functional and packaged dies, each of which serves as a fully packaged IC device 90.

    WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS
    6.
    发明申请
    WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS 审中-公开
    具有互连的WAFER LEVEL INTEGRATION MODULE

    公开(公告)号：WO2009136873A2

    公开(公告)日：2009-11-12

    申请号：PCT/SG2009/000164

    申请日：2009-05-06

    Applicant: VISWANADAM, Gautham

    Inventor： VISWANADAM, Gautham

    IPC: H01L21/328 ,  H01L21/44 ,  H01L21/60

    CPC classification number: H01L29/735 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/11 ,  H01L2924/00

    Abstract: A method and apparatus for manufacturing an integrated circuit (IC) device (90) is disclosed. A wafer (10) is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro-structures (16) that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface (12) of the wafer. The wafer with pre-formed conductive interconnect microstructures (16) are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side (12) devices are fabricated, the silicon material (20) is then removed from a second side (14) of the device wafer (10), opposite the first side, to expose the high temperature conductive interconnect microstructures (16). Contacts are formed on the second side of the device wafer using conductive metal. These contacts are electrically connected to the interior of the microstructures and thereby electrically connect with the functional device (26). The dies 90(1),90(2) are separated along the separation zones (88) between the dies to produce individualized functional and packaged dies, each of which serves as a fully packaged IC device (90).

    Abstract translation: 公开了一种用于制造集成电路（IC）装置（90）的方法和装置。 首先提供具有第一或上表面和第二或底表面的晶片（10）。 晶片可以是空白抛光或未抛光的硅晶片等。 专门设计用于提供管芯级互连配置和映射的高纵横比微结构（16）设置在晶片的第一空白表面（12）上。 具有预先形成的导电互连微结构（16）的晶片被进一步处理用于器件制造，例如在晶片制造设备处。 一旦制造了前侧（12）器件，然后从器件晶片（10）的与第一侧相对的第二侧（14）去除硅材料（20），以暴露高温导电互连微结构（16 ）。 使用导电金属在器件晶片的第二侧上形成触点。 这些触点电连接到微结构的内部，从而与功能器件（26）电连接。 模具90（1），90（2）沿着模具之间的分离区域（88）分离以产生各自的功能和封装的模具，每个模具用作完全封装的IC器件（90）。

    MICRO-DEVICE ON GLASS
    8.
    发明申请
    MICRO-DEVICE ON GLASS 审中-公开
    玻璃上的MICRO-DEVICE

    公开(公告)号：WO2012134394A1

    公开(公告)日：2012-10-04

    申请号：PCT/SG2011/000129

    申请日：2011-03-30

    Applicant: VISWANADAM, Gautham

    Inventor： VISWANADAM, Gautham

    IPC: H01L21/00

    CPC classification number: B81C1/00341 ,  B81B2201/051 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C1/00476 ,  B81C2201/0107 ,  B81C2203/036 ,  H01L21/00

    Abstract: A method of fabricating a micro-device having micro-features on glass is presented. The method includes the steps of preparing a first glass substrate, fabricating a metallic pattern on the first glass substrate, preparing a second glass substrate and providing one or more apertures on the second glass substrate, heating the first glass substrate and the second glass substrate with a controlled temperature raise, bonding the first glass substrate and the second glass substrate by applying pressure to form a bonded substrate, wherein the metallic pattern is embedded within the bonded substrate, cooling the bonded substrate with a controlled temperature drop and thereafter maintaining the bonded substrate at a temperature suitable for etching, etching the metallic pattern within the bonded substrate, wherein an etchant has access to the metallic pattern via the apertures, forming a void within the bonded substrate, wherein the void comprises micro-features.

    Abstract translation: 提出了一种在玻璃上制造具有微特征的微器件的方法。 该方法包括以下步骤：制备第一玻璃基板，在第一玻璃基板上制造金属图案，制备第二玻璃基板并在第二玻璃基板上提供一个或多个孔，加热第一玻璃基板和第二玻璃基板， 控制温度升高，通过施加压力来接合第一玻璃基板和第二玻璃基板以形成接合基板，其中金属图案嵌入在接合基板内，以受控的温度下降冷却接合基板，然后保持接合基板 在适于蚀刻的温度下蚀刻所述键合衬底内的所述金属图案，其中所述蚀刻剂经由所述孔进入所述金属图案，在所述键合衬底内形成空隙，其中所述空隙包括微特征。

    WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS
    9.
    发明申请
    WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS 审中-公开
    具有互连的WAFER LEVEL INTEGRATION MODULE

    公开(公告)号：WO2009136873A3

    公开(公告)日：2010-08-12

    申请号：PCT/SG2009000164

    申请日：2009-05-06

    Applicant: VISWANADAM GAUTHAM

    Inventor： VISWANADAM GAUTHAM

    IPC: H01L21/768

    CPC classification number: H01L29/735 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/11 ,  H01L2924/00

    Abstract: A method and apparatus for manufacturing an integrated circuit (IC) device (90) is disclosed. A wafer (10) is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro- structures (16) that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface (12) of the wafer. The wafer with preformed conductive interconnect microstructures (16) are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side (12) devices are fabricated, the silicon material (20) is then removed from a second side (14) of the device wafer (10), opposite the first side, to expose the high temperature conductive interconnect microstructures (16). Contacts are formed on the second side of the device wafer using conductive metal. These contacts are electrically connected to the interior of the microstructures and thereby electrically connect with the functional device (26). The dies (90(1)),(90(2)) are separated along the separation zones (88) between the dies to produce individualized functional and packaged dies, each of which serves as a fully packaged IC device (90).

    Abstract translation: 公开了一种用于制造集成电路（IC）装置（90）的方法和装置。 首先提供具有第一或上表面和第二或底表面的晶片（10）。 晶片可以是空白抛光或未抛光的硅晶片等。 专门设计用于提供管芯级互连配置和映射的高纵横比微结构（16）设置在晶片的第一空白表面（12）上。 具有预先形成的导电互连微结构（16）的晶片被进一步处理用于器件制造，例如在晶片制造设备处。 一旦制造了前侧（12）器件，然后从器件晶片（10）的与第一侧相对的第二侧（14）去除硅材料（20），以暴露高温导电互连微结构（16 ）。 使用导电金属在器件晶片的第二侧上形成触点。 这些触点电连接到微结构的内部，从而与功能器件（26）电连接。 模具（90（1）），（90（2））沿着模具之间的分离区域（88）分离，以产生各自的功能和封装的模具，每个模具用作完全封装的IC器件（90）。

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