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    INTERRUPTION SYSTEM WITH FLEXIBILITY FOR INTEGRATED CIRCUIT
    1.
    发明专利
    INTERRUPTION SYSTEM WITH FLEXIBILITY FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH1091457A

    公开(公告)日：1998-04-10

    申请号：JP21583097

    申请日：1997-07-25

    Applicant: ZILOG INC

    Inventor： CHAN STEPHEN H

    IPC: G06F9/48 ,  H01L27/02 ,  H01L27/118 ,  G06F9/46

    Abstract: PROBLEM TO BE SOLVED: To provide a microcomputer buried in an integrated circuit with flexible design, in which one interruption input signal is used for servicing to either multiple on-chip or off-chip elements. SOLUTION: A flexible interruption system for supplying interruption signals to the microcontroller 10 provided for the integrated circuit makes a response to either the on-chip or off-chip elements. An interruption circuit is connected to respective bonding pads 30, 32 and 34 and it is also connected to interruption control logic 40 deciding the priority of interruption signals from the elements provided for the chips. All the interruption signals pass common nodes in the interruption circuit. Since a p-channel transistor or an n-channel transistor connected to the common node functions as a pull-up or pull-down transistor, the micro controller 10 senses the rise or fall edge of an interruption request. Since an interruption request signal from either the on-chip element or the off-chip element passes through the common node and the common node is directly connected to a pad, the development and the debugging of a system is simplified.

    LOW VOLTAGE CHARGE PUMP CIRCUIT
    2.
    发明专利
    LOW VOLTAGE CHARGE PUMP CIRCUIT 失效

    公开(公告)号：JPH11265591A

    公开(公告)日：1999-09-28

    申请号：JP35995198

    申请日：1998-12-18

    Applicant: ZILOG INC

    Inventor： TROUTMAN BRUCE LEE

    IPC: G11C16/06 ,  H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To make a low voltage charge pump circuit executable to convert a low voltage to a high voltage using an integrated circuit designed for the operation of a low voltage by constituting the charge pump circuit with a first pump circuit to be connected to a pump oscillator, a level shifting circuit to be connected to the first pump circuit in order to generate an intermediate clock and a second pump circuit to be connected to the level shifting circuit in order to generate a high voltage. SOLUTION: Two clocks operating at different frequencies are made to be generated by providing a pump oscillator PMPOSC- 1 230 and the clock of an HIGH FREQ 240 supplies a timing signal to a low voltage pump circuit CPUMP- LV1 210. The clock of LOW- FREQ 250 supplies a timing signal to a high voltage pump circuit CPUMP- HV1 220. The low voltage pump circuit CPUMP- LV1 210 is supplied to a pump circuit having a frequency higher than that of the high voltage pump circuit CPUMP- HV1 220 and the low voltage pump circuit CPUMP- LV1 210 can replenish electric charge lossed in the process of a voltage conversion.

    I/O PORT AND TECHNIQUE FOR DESIGNATING ADDRESS OF RAM MEMORY
    3.
    发明专利
    I/O PORT AND TECHNIQUE FOR DESIGNATING ADDRESS OF RAM MEMORY 失效

    公开(公告)号：JPH10198624A

    公开(公告)日：1998-07-31

    申请号：JP23181897

    申请日：1997-08-12

    Applicant: ZILOG INC

    Inventor： OSCAR EISENBERG

    IPC: G06F13/14 ,  G06F12/06 ,  G06F13/42

    Abstract: PROBLEM TO BE SOLVED: To perform access to an I/O port exceeding the I/O address designation ability of microprocessor by writing data in the area of selected I/O port bus when an I/O port access code is detected. SOLUTION: An extension I/O port interface 42 monitors a code in the operating mode area of ROM address bus 22 and detects whether the I/O port access code exists in the area or not. An RDROM control signal 20 is monitored and it is detected whether a signal is in a read ROM state or not. The address of I/O port address area is decoded and any special I/O port is selected out of extension I/O ports 40 to write data. When an RDROM control signal 22 is in the read ROM state and the I/O port access code exists in the operating mode area of ROM address bus 22, the interface 42 writes data through a control line 46 into the selected I/O port.

    GATE DIELECTRIC OF FET AND ITS FORMING METHOD
    7.
    发明专利
    GATE DIELECTRIC OF FET AND ITS FORMING METHOD 失效

    公开(公告)号：JPH11126901A

    公开(公告)日：1999-05-11

    申请号：JP22705598

    申请日：1998-08-11

    Applicant: ZILOG INC

    Inventor： BERG JOHN E

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/318 ,  H01L29/51

    Abstract: PROBLEM TO BE SOLVED: To provide a gate dielectric having good characteristics, such as high dielectric breakdown strength, immunity against hot carrier transfer, and barrier effect with respect to boron diffusion, in which the gate dielectric is operated at an applying-voltage/film-layer ratio between dielectric parts smaller than that of SiO2 . SOLUTION: In an insulating field effect transistor(FET), a thermally grown oxide silicon layer 12 for covering at least part of a transistor channel region 3, and a nitride silicon layer 14 for covering at least part of a first oxide silicon layer are deposited through a low pressure chemical vapor deposition(LPCVD) method. An abrupt heat treatment step is carried out to form a second oxide layer for covering at least part of the nitride silicon layer and change the surface part of the second oxide layer to a dioxide surface layer. In this way, a gate dielectric 10 with an oxide-nitride-oxide structure has a high dielectric breakdown strength and other characteristics mentioned.

    Frequency locked loop
    10.
    发明申请
    Frequency locked loop 有权
    锁频环路

    公开(公告)号：US20040090277A1

    公开(公告)日：2004-05-13

    申请号：US10690874

    申请日：2003-10-21

    Applicant: ZiLOG, Inc.

    Inventor： Anatoliy V. Tsyrganovich

    IPC: H03B001/00

    CPC classification number: H03L7/085 ,  H03D13/001 ,  H03L7/091

    Abstract: A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

    Abstract translation: 微控制器集成电路中的锁相环具有精确的数字反馈控制回路。 频率锁定环执行时钟相乘功能，使得便宜且低频的外部晶体可用于以较高频率和低抖动时钟信号来对微控制器的处理器进行时钟控制，并且以一个 低频时基是2赫兹的倍数。 在一个实施例中，数字反馈控制回路包括斜坡发生器，数字滤波器和环路分频器。 当频率锁定过程进行频率锁定时，斜坡发生器被控制以输出更陡峭和更陡峭的斜坡。 改变预置环路分频器的预设值，以相对于参考输入信号调整反馈信号的相位。

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