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公开(公告)号：KR1019990051281A
公开(公告)日：1999-07-05
申请号：KR1019970070565
申请日：1997-12-19
IPC: H04L12/407
Abstract: 1. 청구범위에 기재된 발명이 속한 기술분야
본 발명은 상호운용성 검증을 위한 분산 시험 방법에 관한 것임.
2. 발명이 해결하려고 하는 기술적 과제
본 발명은 시험 서버가 시험 데이터베이스에서 시험 코드를 추출한 후에 통신망을 통하여 시험 대상 시스템에 탑재하여, 시험 소프트웨어가 분산되어 수행되도록 한 분산 시험 방법을 제공하는데 그 목적이 있음.
3. 발명의 해결방법의 요지
본 발명은, 시험에 필요한 시험 소프트웨어 코드를 각 시험 유형별로 데이터베이스로 구축하고 이를 시험 서버를 통하여 상호운용성 검증을 요구하는 각 시험 대상 시스템에 탑재되게 하여, 즉 시험을 위한 기능이 데이터베이스내에 구축된 소프트웨어 코드로 구성되고 이 소프트웨어 코드를 시험을 요구하는 시험 대상 시스템으로 전달하여 탑재되게 하여, 분산 시험이 가능하게 한다.
4. 발명의 중요한 용도
본 발명은 통신망을 이용한 분산 시험에 이용됨.-
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公开(公告)号：KR1019910008758B1
公开(公告)日：1991-10-19
申请号：KR1019890003068
申请日：1989-03-11
CPC classification number: Y02D50/20
Abstract: The line terminator deposited between the subscriber lines and the ISDN test exchange. The line terminator includes a line driver (10) for transmitting the subscriber information and signalling type information to the ISDN test exchange, for supplying power to a narrow band interface unit and for controlling the narrow band interface unit by reversing the polarity of the power, an U-tranceiver (20) for receiving and transmitting the subscriber information and the signalling method information to a time dividing switch to a LT control unit (2) respectively, a D- channel driver (30) for executing data communication with the U-tranceiver using the HDLC loop method and for transmitting the processed information to the LT controller (2), and a processor interface unit (40) for controlling the I/O information of the D- channel driver.
Abstract translation: 线路终端器存放在用户线路和ISDN测试交换机之间。 线路终端器包括用于将用户信息和信令类型信息发送到ISDN测试交换机的线路驱动器（10），用于向窄带接口单元供电并通过反转功率的极性来控制窄频带接口单元， 用于分别向LT控制单元（2）向时间分配开关发送用户信息和信令方法信息的U型收发器（20），用于与U控制单元执行数据通信的D信道驱动器（30） 使用HDLC循环方法并将处理的信息发送到LT控制器（2）的处理器接口单元（40），用于控制D通道驱动器的I / O信息。
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Patent Agency Ranking
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公开(公告)号：KR1019960002685B1
公开(公告)日：1996-02-24
申请号：KR1019920026066
申请日：1992-12-29
IPC: H04L12/28
Abstract: a transmitting part having a scrambler which scrambles 48 byte payload of 53 bytes cells in byte unit, a parallel HEC(header error control) encoder which receives an initial 4 bytes of 5 bytes cell header in the byte unit to generate the HEC and inserts the generated HEC into the fifth byte, and a transmitting controller which controls the scrambler and the parallel HEC encoder; a receiving part having a parallel HEC reverse encoder which controls a cell boundary extraction and error in a cell header from the data in the byte unit transmitted to a physical medium connector, a reverse scrambler which restores an original cell payload from the scrambled 48 byte payload, and a receiving controller which controls the parallel HEC reverse encoder and the reverse scrambler; and command and state registers each connected to the transmitting controller and the receiving controller.
Abstract translation: 发送部分具有加扰器，其以字节为单位加扰53字节的48字节有效载荷;并行HEC（报头错误控制）编码器，其接收字节单元中的初始4字节的5字节的单元头部，以生成HEC并插入 生成HEC到第五字节，以及控制加扰器和并行HEC编码器的发送控制器; 接收部分具有并行HEC反向编码器，其从发送到物理介质连接器的字节单元中的数据控制单元报头中的单元边界提取和错误;反向加扰器，其从加扰的48字节有效载荷恢复原始单元净荷 以及控制并行HEC反向编码器和反向扰频器的接收控制器; 每个连接到发送控制器和接收控制器的命令和状态寄存器。
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公开(公告)号：KR1019960001056B1
公开(公告)日：1996-01-17
申请号：KR1019930018907
申请日：1993-09-17
Inventor： 이숭희
IPC: H04L12/00
Abstract: a cell input processor for extracting fields for control by temporarily inputting an input ATM cell in one cell unit time and sparing any time for a control process; an imaginary connected discrimination translating unit for converting an imaginary connected discriminator into a specific address of a memory in order to find out the input cell to be inputted the input cell processor; a parameter storage memory for inputting a cell/octet timing signal and storing a traffic parameter to be used for controlling the specific address; a determination logic circuit for comparing the stored cell parameter with a real parameter, and outputting a determined signal according to the result of the comparison; and a cell output processing unit for outputting a cell packet and tagging of the cell input processing unit under use of the resulted signal from the determination logic circuit and the priority of cell damage.
Abstract translation: 一个单元输入处理器，用于通过在一个单元单元时间内临时输入输入的ATM信元来提取用于控制的字段，并且随时随地进行控制处理; 虚拟连接鉴别转换单元，用于将虚拟连接的鉴别器转换成存储器的特定地址，以便找出要输入的输入单元处理器的输入单元; 用于输入单元/八位字节定时信号并存储要用于控制该特定地址的业务参数的参数存储存储器; 确定逻辑电路，用于将存储的单元参数与实参参数进行比较，并根据比较结果输出确定的信号; 以及单元输出处理单元，用于在使用来自确定逻辑电路的结果信号和单元损坏的优先级的情况下输出单元包和单元输入处理单元的标记。
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