Abstract:
A transistor of SiC comprises superimposed a drain (13), a highly doped substrate layer (1), a low doped n-type drift layer (2), a p-type base layer being divided into a first lower highly doped base sub-layer (3) and an upper low doped second base sub-layer (4) on top thereof, a highly doped n-type source region layer (6) and a source (11). It also has an insulating layer (8) with a gate electrode (9) thereon arranged on top of the base layer and extending laterally from the source region layer to a n-type layer (7) connected to the drift layer.
Abstract:
A semiconductor device of planar structure, consisting of doped silicon carbide (SiC), comprising a pn junction, formed of a first conducting type layer (1) and on top thereof of a second conducting type layer (2), the edge of the second of said layers being provided with an edge termination (JTE) (3), enclosing stepwise or continuously decreasing effective sheet charge density towards the outer border of the termination, where the pn junction and its JTE are covered by a third layer (4).
Abstract:
A bipolar transistor having at least a low doped drift layer (14) of crystalline SiC comprises at least one first layer (13) of a semiconductor material having a wider energy gap between the conduction band and the valence band than an adjacent layer (14) of SiC.
Abstract:
A bipolar transistor having at least a low doped drift layer (14) of crystalline SiC comprises at least one first layer (13) of a semiconductor material having a wider energy gap between the conduction band and the valence band than an adjacent layer (14) of SiC.
Abstract:
A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers and where the edge of the higher doped conducting layer of the pn junction exhibits a charge profile with a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the main pn junction to a zero or almost zero total charge or charge density at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.
Abstract:
A field controlled semiconductor device of SiC comprises superimposed in the order mentioned at least a drain (12), a highly doped substrate layer (1) and a low doped n-type drift layer (2). It has also a highly doped n-type source region layer (6) and a source (11) connected thereto. A doped channel region layer (4) connects the source region layer to the drift layer, and a current is intended to flow therethrough when the device is in an on-state. The device has also a gate electrode (9). The channel region layer has a substantially lateral extension and is formed by a low doped n-type layer (4). The gate electrode (9) is arranged to influence the channel region layer from above for giving a conducting channel (17) created therein from the source region layer to the drift layer a substantially lateral extension.
Abstract:
A transistor of SiC for high voltage and high switching frequency applications is a MISFET or an IGBT. This transistor comprises a plurality of laterally spaced active regions (16). The center to center distance of two adjacent active regions defines a lateral width of a cell of the transistor. The relation of the lateral width (Wa) of an accumulation region defined as the region in the drift layer connecting to a gate-insulating layer (11) in each individual cell and the lateral cell width (Wc) is selected so as to keep the power losses in the transistor as a consequence of switching below a determined proportion to the power losses relating to conduction of the transistor for a predetermined switching frequency and on-state voltage for which the transistor is designed.
Abstract:
A semiconductor device of SiC is adapted to hold high voltages in the blocking state thereof. The device comprises two parts (1, 2) each comprising one or more semiconductor layers of SiC and connected in series between two opposite terminals of the device, namely a sub-semiconductor device (1) able to withstand only low voltages in the blocking state thereof and a voltage-limiting part (2) able to withstand high voltages in the blocking state of the device and adapted to protect said sub-semiconductor device by taking a major part of the voltage over the device in the blocking state thereof.
Abstract:
A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers, where the junction is at the edge of the lower doped conducting layer terminated by a depletion region stopper (DRS) which exhibits a charge profile with a stepwise or uniformly increasing total charge and/or effective sheet charge density from a first lowest value to a highest value at the outermost edge (5) of the junction following a radial direction from the main junction towards the outermost edge.
Abstract:
A field controlled semiconductor device of SiC comprising superimposed in the order mentioned a drain (15), a highly doped substrate layer (1), a highly doped n-type buffer layer (2) and a low doped n-type drift layer (3). It also has a highly doped n-type source region layer (7) and a source (14) connected thereto, a vertical trench (9) from above, a low doped n-type channel region layer (6) extending vertically along a wall (11) of said trench and connecting said source region layer to said drift layer and through which a current is intended to flow when the device is in an on-state. A gate electrode (12) is arranged in said trench at least along said wall and to, upon applying a voltage thereto, influence the charge carrier distribution of said channel region layer and by that the conductivity thereof. The device comprises further a p-type base layer (4) arranged laterally next to said channel region layer at the opposite side thereof with respect to the gate electrode for forming a vertical conducting channel in said channel region layer at a distance from said trench wall.