公开(公告)号：WO2010005526A1

公开(公告)日：2010-01-14

申请号：PCT/US2009/003898

申请日：2009-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  MULFINGER, Robert ,  SCHEIPER, Thilo ,  KAMMLER, Thorsten

Inventor： WEI, Andy ,  MULFINGER, Robert ,  SCHEIPER, Thilo ,  KAMMLER, Thorsten

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas (211D, 211S), the fins (210) and isolation structures (208A) in a self- aligned manner within a bulk semiconductor material. After defining the basic fin structures (210), highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

Abstract translation: 可以基于增强的掩蔽状态形成诸如FinFETS和三栅极晶体管的三维晶体管结构，从而能够形成漏极和源极区域（211D，211S），鳍片（210）和隔离结构（208A） ）以体积半导体材料中的自对准方式。 在定义了基本的翅片结构（210）之后，可以使用平面晶体管配置的高效制造技术，从而进一步提高三维晶体管配置的整体性能。

公开(公告)号：WO2007053382A1

公开(公告)日：2007-05-10

申请号：PCT/US2006/041560

申请日：2006-10-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOENTSCHEL, Jan ,  WEI, Andy ,  HORSTMANN, Manfred ,  KAMMLER, Thorsten

Inventor： HOENTSCHEL, Jan ,  WEI, Andy ,  HORSTMANN, Manfred ,  KAMMLER, Thorsten

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78639 ,  H01L29/78654

Abstract: By forming a deep recess (111, 211) through the buried insulating layer (103, 203) and re-growing a strained semiconductor material (112, 212), an enhanced strain generation mechanism may be provided in SOI- like transistors (100, 200). Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract translation: 通过形成通过掩埋绝缘层（103,203）的深凹槽（111,211）并重新生长应变半导体材料（112,212），增强的应变产生机构可以设置在类SOI晶体管（100， 200）。 因此，也可以通过整个有源层上的嵌入的应变半导体材料有效地产生应变，从而显着提高可以限定两个沟道区的晶体管器件的性能。

公开(公告)号：WO2006083546A2

公开(公告)日：2006-08-10

申请号：PCT/US2006/001596

申请日：2006-01-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  WEI, Andy ,  BIERSTEDT, Helmut

Inventor： KAMMLER, Thorsten ,  WEI, Andy ,  BIERSTEDT, Helmut

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/26586 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: By performing a sequence of selective epitaxial growth processes with at least two different species, or by introducing a first dopant species prior to the epitaxial growth of a drain and source region, a halo region may be formed in a highly efficient manner, while at the same time the degree of lattice damage in the epitaxially grown semiconductor region is maintained at a low level. The method ??? forming a first semiconductor region 211 by a first epitaxial growth process, forming a second semiconductor region 210 by performing a second epitaxial growth process, whereas the first and second semiconductor regions compose different dopant species.

Abstract translation: 通过用至少两种不同的物质执行一系列选择性外延生长过程，或者通过在漏极和源极区的外延生长之前引入第一掺杂物种，可以以高效的方式形成晕圈，而在 同时，外延生长的半导体区域中的晶格损伤程度保持在低水平。 方法 ？？？ 通过第一外延生长工艺形成第一半导体区域211，通过执行第二外延生长工艺形成第二半导体区域210，而第一和第二半导体区域构成不同的掺杂物质。

公开(公告)号：WO2007100589A1

公开(公告)日：2007-09-07

申请号：PCT/US2007/004544

申请日：2007-02-20

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: By removing a portion of a halo region (206, 306) or by avoiding the formation of the halo region (206, 306) within the extension region (209A), which may be subsequently formed on the basis of a re-grown semiconductor material (218, 318), the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

Abstract translation: 通过去除一部分卤素区域（206,306）或通过避免在扩展区域（209A）内形成卤区域（206,306），其可以随后基于重新生长的半导体材料形成 （218,318），可以显着改善阈值滚降行为，其中可以同时实现增强的电流驱动能力。

公开(公告)号：WO2006118799A1

公开(公告)日：2006-11-09

申请号：PCT/US2006/014781

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  BIERSTEDT, Helmut ,  LUNING, Scott, D.

Inventor： KAMMLER, Thorsten ,  BIERSTEDT, Helmut ,  LUNING, Scott, D.

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L29/7833 ,  H01L21/0206 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78621

Abstract: A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

Abstract translation: 第一栅极结构和第二栅极结构形成在半导体衬底上。 第一保护层形成在第一栅极结构和相关源极漏极区之上。 在去除第一保护层之前，在第二源极漏极上形成第一外延层。

公开(公告)号：WO2005098929A2

公开(公告)日：2005-10-20

申请号：PCT/US2005/010475

申请日：2005-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  LENSKI, Markus ,  GRAETSCH, Falk ,  REICHEL, Carsten ,  SCHWAN, Christoph ,  BIERSTEDT, Helmut ,  KAMMLER, Thorsten ,  MAZUR, Martin

Inventor： LENSKI, Markus ,  GRAETSCH, Falk ,  REICHEL, Carsten ,  SCHWAN, Christoph ,  BIERSTEDT, Helmut ,  KAMMLER, Thorsten ,  MAZUR, Martin

IPC: H01L21/336

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: The present invention allows the formation of sidewall spacers (217,218) adjacent a feature (206) on a substrate (201) without there being an undesirable erosion of the feature. The feature (206) is covered by one or more protective layers (220,207). A layer of a spacer material (211) is deposited over the feature (206) and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers (220, 207) are substantially not affected by the etchant. Thus, the one or more protective layers (220, 207) protect the feature from being exposed to the etchant.

Abstract translation: 本发明允许在衬底（201）上邻近特征（206）形成侧壁间隔物（217,218），而不会有不希望的特征侵蚀。 特征（206）由一个或多个保护层（220,207）覆盖。 隔离材料层（211）沉积在特征（206）上并各向异性地蚀刻。 在各向异性蚀刻中使用的蚀刻剂适于选择性地去除间隔物材料，而一个或多个保护层（220,207）基本上不受蚀刻剂的影响。 因此，一个或多个保护层（220,207）保护特征不暴露于蚀刻剂。

公开(公告)号：WO2005045924A1

公开(公告)日：2005-05-19

申请号：PCT/US2004/031038

申请日：2004-09-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  VAN BENTUM, Ralf ,  LUNING, Scott ,  KAMMLER, Thorsten

Inventor： VAN BENTUM, Ralf ,  LUNING, Scott ,  KAMMLER, Thorsten

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L29/665 ,  H01L29/66628

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract translation: 可以对于不同的器件区域单独地调整极限比例的半导体器件中的外延生长的半导体区域的高度，因为可以执行两个或更多个外延生长步骤，其中外延生长掩模选择性地抑制在指定器件中形成半导体区域 地区。 在其他实施例中，公共外延生长工艺可以用于两个或更多个不同的器件区域，随后可以在所选择的器件区域上执行选择性氧化工艺，以便精确地降低所选区域中先前外延生长的半导体区域的高度 。

公开(公告)号：WO2008094653A2

公开(公告)日：2008-08-07

申请号：PCT/US2008/001292

申请日：2008-01-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  GEHRING, Andreas ,  WIATR, Maciej ,  WEI, Andy ,  KAMMLER, Thorsten ,  SCOTT, Casey ,  BOSCHKE, Roman

Inventor： GEHRING, Andreas ,  WIATR, Maciej ,  WEI, Andy ,  KAMMLER, Thorsten ,  SCOTT, Casey ,  BOSCHKE, Roman

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal suicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract translation: 通过在高锗浓度的硅/锗材料上提供保护层，应变半导体材料的相应损失可以被显着降低或甚至完全避免。 保护层可以在临界清洁工艺之前形成并且可以保持直到形成金属硅化物区域。 因此，P型晶体管的高性能增益可以在选择性外延生长工艺期间不需要大量的溢出而实现。

公开(公告)号：WO2006137963A1

公开(公告)日：2006-12-28

申请号：PCT/US2006/014696

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  BROWN, David, E. ,  EN, William, George ,  KAMMLER, Thorsten ,  BESSER, Paul, R. ,  LUNING, Scott, D.

Inventor： BROWN, David, E. ,  EN, William, George ,  KAMMLER, Thorsten ,  BESSER, Paul, R. ,  LUNING, Scott, D.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling suicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent control of the placement of these features for optimizing device performance. The methodology utilizes multiple spacers to decrease current crowding effects in devices due to proximity effects between LDD and deep S/D regions in reduced architecture devices.

Abstract translation: 提出了集成方案，其提供了相对于选择性外延生长（SEG）引发的S / D区域去耦合深源/漏（S / D）植入物的放置，以及相对于升高的S / D去耦自杀放置 特征。 这些集成方案可以以多种方式组合，以允许独立控制这些特征的放置以优化装置性能。 该方法利用多个间隔物来减少由于减少的架构设备中LDD与深S / D区域之间的邻近效应而导致的器件中的电流拥挤效应。

公开(公告)号：WO2006118786A1

公开(公告)日：2006-11-09

申请号：PCT/US2006/014627

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  WEI, Andy ,  LENSKI, Markus

Inventor： KAMMLER, Thorsten ,  WEI, Andy ,  LENSKI, Markus

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

Abstract: By removing an outer spacer 109, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal suicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer 115 may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Abstract translation: 通过去除用于形成高度复杂的横向掺杂剂分布的外部间隔物109，在形成金属硅化物之前，可以获得与常规方法的高度的工艺相容性，而同时接触衬里层115可以是 定位得更靠近通道区域，从而允许用于在通道区域中产生相应应变的高效应力传递机构。