公开(公告)号：WO2010037523A1

公开(公告)日：2010-04-08

申请号：PCT/EP2009/007002

申请日：2009-09-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  KRONHOLZ, Stephan ,  LENSKI, Markus ,  WEI, Andy ,  OTT, Andreas

Inventor： KRONHOLZ, Stephan ,  LENSKI, Markus ,  WEI, Andy ,  OTT, Andreas

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: A strain inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments, by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain inducing semiconductor material may be reduced, while nevertheless providing for a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, p-channel transistors may have a silicon/germanium alloy with a hexagonal shape thereby significantly enhancing the overall strain transfer efficiency.

Abstract translation: 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层，例如二氧化硅材料来保持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，p沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

公开(公告)号：WO2007100589A1

公开(公告)日：2007-09-07

申请号：PCT/US2007/004544

申请日：2007-02-20

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: By removing a portion of a halo region (206, 306) or by avoiding the formation of the halo region (206, 306) within the extension region (209A), which may be subsequently formed on the basis of a re-grown semiconductor material (218, 318), the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

Abstract translation: 通过去除一部分卤素区域（206,306）或通过避免在扩展区域（209A）内形成卤区域（206,306），其可以随后基于重新生长的半导体材料形成 （218,318），可以显着改善阈值滚降行为，其中可以同时实现增强的电流驱动能力。

公开(公告)号：WO2010002448A1

公开(公告)日：2010-01-07

申请号：PCT/US2009/003877

申请日：2009-06-30

Applicant: ADVANCED MICRO DEVICES, INC ,  HOENTSCHEL, Jan ,  GRIEBENOW, Uwe ,  WEI, Andy

Inventor： HOENTSCHEL, Jan ,  GRIEBENOW, Uwe ,  WEI, Andy

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785

Abstract: A non-conformal metal suicide layer (156) in a transistor (150) of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal (156) may be used.

Abstract translation: 在凹陷漏极和源极配置的晶体管（150）中的非保形金属硅化物层（156）可以提供相对于应变诱导机构，漏极/源极电阻等的增强的效率。 为此，在一些情况下，可以在硅化工艺之前进行非晶化注入工艺，而在其它情况下可以使用难熔金属（156）的各向异性沉积。

公开(公告)号：WO2009032230A3

公开(公告)日：2009-03-12

申请号：PCT/US2008/010299

申请日：2008-08-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  WAITE, Andrew ,  TRENTZSCH, Martin ,  GROSCHOPF, Johannes ,  GRASSHOFF, Gunter ,  OTT, Andreas

Inventor： WEI, Andy ,  WAITE, Andrew ,  TRENTZSCH, Martin ,  GROSCHOPF, Johannes ,  GRASSHOFF, Gunter ,  OTT, Andreas

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: In the process sequence for replacing conventional gate electrode structures (310) by high-k metal gate structures (310N, 310B, 310P), the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps (322, 325, 327, 331), thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain- inducing mechanisms in the transistor level as well as in the contact level.

公开(公告)号：WO2008094653A2

公开(公告)日：2008-08-07

申请号：PCT/US2008/001292

申请日：2008-01-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  GEHRING, Andreas ,  WIATR, Maciej ,  WEI, Andy ,  KAMMLER, Thorsten ,  SCOTT, Casey ,  BOSCHKE, Roman

Inventor： GEHRING, Andreas ,  WIATR, Maciej ,  WEI, Andy ,  KAMMLER, Thorsten ,  SCOTT, Casey ,  BOSCHKE, Roman

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal suicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract translation: 通过在高锗浓度的硅/锗材料上提供保护层，应变半导体材料的相应损失可以被显着降低或甚至完全避免。 保护层可以在临界清洁工艺之前形成并且可以保持直到形成金属硅化物区域。 因此，P型晶体管的高性能增益可以在选择性外延生长工艺期间不需要大量的溢出而实现。

公开(公告)号：WO2008054679A1

公开(公告)日：2008-05-08

申请号：PCT/US2007/022682

申请日：2007-10-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  GEHRING, Andreas ,  WEI, Andy ,  MOWRY, Anthony ,  RATHOR, Manuj

Inventor： GEHRING, Andreas ,  WEI, Andy ,  MOWRY, Anthony ,  RATHOR, Manuj

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

Abstract translation: 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区域，第二晶体管元件包括至少一个第二非晶区域。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，执行第二退火处理。 应力产生层在第二退火处理期间保留在半导体衬底上。

公开(公告)号：WO2006118786A1

公开(公告)日：2006-11-09

申请号：PCT/US2006/014627

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  WEI, Andy ,  LENSKI, Markus

Inventor： KAMMLER, Thorsten ,  WEI, Andy ,  LENSKI, Markus

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

Abstract: By removing an outer spacer 109, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal suicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer 115 may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Abstract translation: 通过去除用于形成高度复杂的横向掺杂剂分布的外部间隔物109，在形成金属硅化物之前，可以获得与常规方法的高度的工艺相容性，而同时接触衬里层115可以是 定位得更靠近通道区域，从而允许用于在通道区域中产生相应应变的高效应力传递机构。

公开(公告)号：WO2010005526A1

公开(公告)日：2010-01-14

申请号：PCT/US2009/003898

申请日：2009-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  MULFINGER, Robert ,  SCHEIPER, Thilo ,  KAMMLER, Thorsten

Inventor： WEI, Andy ,  MULFINGER, Robert ,  SCHEIPER, Thilo ,  KAMMLER, Thorsten

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas (211D, 211S), the fins (210) and isolation structures (208A) in a self- aligned manner within a bulk semiconductor material. After defining the basic fin structures (210), highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

Abstract translation: 可以基于增强的掩蔽状态形成诸如FinFETS和三栅极晶体管的三维晶体管结构，从而能够形成漏极和源极区域（211D，211S），鳍片（210）和隔离结构（208A） ）以体积半导体材料中的自对准方式。 在定义了基本的翅片结构（210）之后，可以使用平面晶体管配置的高效制造技术，从而进一步提高三维晶体管配置的整体性能。

公开(公告)号：WO2010002447A1

公开(公告)日：2010-01-07

申请号：PCT/US2009/003876

申请日：2009-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SALZ, Heike

Inventor： WEI, Andy ,  HOENTSCHEL, Jan ,  SALZ, Heike

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L29/7845 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/41758 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: Scalability of a strain-inducing mechanism on the basis of a stressed dielectric overlayer may be enhanced by forming a single stress-inducing layer (230) in combination with contact trenches, which may shield a significant amount of a non-desired stress component in the complementary transistor (220, 220P), while also providing a strain component in the transistor width direction (220W)when the contact material may be provided with a desired internal stress level.

Abstract translation: 可以通过与接触沟槽组合形成单个应力诱导层（230）来增强基于应力电介质覆盖层的应变诱导机构的可伸缩性，其可以屏蔽大量的非期望应力分量 互补晶体管（220,220P），同时当可以提供所需的内部应力水平时，还在晶体管宽度方向（220W）上提供应变分量。

公开(公告)号：WO2008094666A2

公开(公告)日：2008-08-07

申请号：PCT/US2008/001310

申请日：2008-01-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  GEHRING, Andreas ,  HOENTSCHEL, Jan ,  WEI, Andy

Inventor： GEHRING, Andreas ,  HOENTSCHEL, Jan ,  WEI, Andy

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

Abstract: A substrate diode for an SOI device (200, 300) is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings (21 IA, 21 IB, 31 IA, 311B) for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure (236, 336) used for defining the drain and source regions (237, 337), thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers (236, 336) in the transistor devices (230A, 230B, 330A, 33OB). In a further aspect, in addition to or alternatively, an offset spacer (360S) may be formed substantially without affecting the configuration of respective transistor devices (230A, 230B, 330A, 33OB).

Abstract translation: 根据适当设计的制造流程形成用于SOI器件（200,300）的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面中，用于衬底二极管的相应开口（21A，21B，31A，311B）可以在形成用于限定漏极和源极区域（237,213）的对应侧壁间隔结构（236,336）之后形成， 337），从而获得二极管区域中的掺杂剂的显着的横向分布，其因此可以在随后的硅化步骤期间提供足够的工艺余量，其基础是去除晶体管器件（230A，230B）中的间隔物（236,336） 230B，330A，33OB）。 在另一方面，除了或者可选地，可以基本上不形成相应的晶体管器件（230A，230B，330A，33B）的配置来形成偏移间隔物（360S）。