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    METHOD FOR REDUCING CONTACT DEFECTS IN SEMICONDUCTOR CELLS
    1.
    发明申请
    METHOD FOR REDUCING CONTACT DEFECTS IN SEMICONDUCTOR CELLS 审中-公开
    减少半导体电池中接触缺陷的方法

    公开(公告)号：WO2004053980A1

    公开(公告)日：2004-06-24

    申请号：PCT/US2003/029985

    申请日：2003-09-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HUI, Angela, T. ,  LI, Wenmei ,  TU, Amy, C.

    IPC: H01L21/768

    CPC classification number: H01L21/76802

    Abstract: A method and system for providing at least One contact in a semiconductor device is described. The semiconductor device includes a substrate (201), an etch stop layer (240), an interlayer dielectric (250) on the etch stop layer (240), an anti-reflective coating (ARC) layer (260) on the interlayer dielectric (250), and at least one feature below the etch stop layer (240). A resist mask having an aperture and residing on the ARC layer (260) is provided. The aperture is above an exposed portion of the ARC layer (260). The method and system include etching the exposed ARC layer (260) and the underlying interlayer dielectric (250) without etching through the etch stop layer (240), thereby providing a portion of at least one contact hole. The method and system also include removing the resist mask in situ, removing a portion of the etch stop layer (240) exposed in the portion of the contact hole, and filling the contact hole with a conductive material.

    Abstract translation: 描述了一种用于在半导体器件中提供至少一个触点的方法和系统。 半导体器件包括衬底（201），蚀刻停止层（240），蚀刻停止层（240）上的层间电介质（250），层间电介质上的抗反射涂层（ARC）层（260） 250），以及蚀刻停止层（240）下方的至少一个特征。 提供了具有孔并且驻留在ARC层（260）上的抗蚀剂掩模。 孔径在ARC层（260）的暴露部分之上。 该方法和系统包括蚀刻暴露的ARC层（260）和下层层间电介质（250），而不通过蚀刻停止层（240）进行蚀刻，从而提供至少一个接触孔的一部分。 所述方法和系统还包括在原位移除抗蚀剂掩模，去除在接触孔的部分中露出的蚀刻停止层（240）的一部分，并用导电材料填充接触孔。

    METHOD OF FORMING PLANARIZED SHALLOW TRENCH ISOLATION
    2.
    发明申请
    METHOD OF FORMING PLANARIZED SHALLOW TRENCH ISOLATION 审中-公开
    形成平面浅层分离分离方法

    公开(公告)号：WO2005074023A1

    公开(公告)日：2005-08-11

    申请号：PCT/US2004/043108

    申请日：2004-12-21

    Applicant: ADVANCED MICRO DEVICES, INC. ,  CHAN, Darin, A. ,  CHAN, Simon, S. ,  HUI, Angela, T.

    Inventor： CHAN, Darin, A. ,  CHAN, Simon, S. ,  HUI, Angela, T.

    IPC: H01L21/762

    CPC classification number: H01L21/76224

    Abstract: Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill (25) with respect to the polish stop film (23) prior to removing the polish stop film (23). Embodiments include etching back a silicon oxide trench fill (25) to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer (23) leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.

    Abstract translation: 在去除抛光停止膜（23）之前，通过相对于抛光停止膜（23）选择性地蚀刻介质沟槽填充物（25）来形成具有最小化形貌的平坦化STI。 实施例包括将氧化硅沟槽填充物（25）刻蚀至约至大约的深度，然后剥离留下基本平坦化表面的氮化硅抛光停止层（23），从而提高后续栅电极的精度 图案化和缩小桁条。

    METHOD OF SHRINKING AN INTEGRATED CIRCUIT GATE
    6.
    发明申请
    METHOD OF SHRINKING AN INTEGRATED CIRCUIT GATE 审中-公开
    收集集成电路门的方法

    公开(公告)号：WO2002078071A2

    公开(公告)日：2002-10-03

    申请号：PCT/US2001/048596

    申请日：2001-12-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HUI, Angela, T. ,  GRANDEHARI, Kouros ,  SINGH, Bhanwar

    IPC: H01L21/28

    CPC classification number: H01L21/28123 ,  H01L21/32139

    Abstract: An exemplary method of fabricating an integrated circuit includes patterning a first layer (28) having a first dimension where the first layer (28) is disposed over an etch stop layer (26) and a second layer (24); oxidizing the surface (30) of the patterned first layer (28); removing the oxidized surface (30) of the patterned first layer (28) resulting in a second dimension for the patterned first layer (28); and etching the etch stop layer (26) and the second layer (24) using the patterned first layer (28) having the second dimension as a hard mask.

    Abstract translation: 制造集成电路的示例性方法包括图案化具有第一尺寸的第一层（28），其中第一层（28）设置在蚀刻停止层（26）和第二层（24）之上; 氧化图案化的第一层（28）的表面（30）; 去除图案化的第一层（28）的氧化表面（30），导致图案化的第一层（28）的第二尺寸; 以及使用具有第二维度的图案化的第一层（28）作为硬掩模来蚀刻蚀刻停止层（26）和第二层（24）。

    IN-SITU SURFACE TREATMENT FOR MEMORY CELL FORMATION
    8.
    发明申请
    IN-SITU SURFACE TREATMENT FOR MEMORY CELL FORMATION 审中-公开
    用于记忆细胞形成的现场表面处理

    公开(公告)号：WO2005104187A1

    公开(公告)日：2005-11-03

    申请号：PCT/US2005/004654

    申请日：2005-02-11

    Applicant: ADVANCED MICRO DEVICES, INC. ,  HUI, Angela, T.

    Inventor： HUI, Angela, T.

    IPC: H01L21/00

    CPC classification number: H01L21/67069

    Abstract: A system and methodology are disclosed for forming a passive layer on a conductive layer, such as can be done during fabrication of an organic memory cell, which generally mitigates drawbacks inherent in conventional inorganic memory devices. The passive layer includes a conductivity facilitating compound, such as copper sulfide (Cu 2 S), which is generated from an upper portion of a conductive material. The conductive material can serve as a bottom electrode in the memory cell, and the upper portion of the conductive material can be transformed into the passive layer via treatment with a plasma generated from fluorine (F) based gases.

    Abstract translation: 公开了用于在导电层上形成钝化层的系统和方法，例如可以在制造有机存储器单元期间完成，这通常减轻了常规无机存储器件固有的缺点。 钝化层包括从导电材料的上部产生的导电性促进化合物，例如硫化铜（Cu2S）。 导电材料可以用作存储单元中的底部电极，并且导电材料的上部可以通过用基于氟（F）的气体产生的等离子体处理而转化为钝化层。

    MEMORY WORDLINE HARD MASK EXTENSION
    10.
    发明申请
    MEMORY WORDLINE HARD MASK EXTENSION 审中-公开

    公开(公告)号：WO2003083916A1

    公开(公告)日：2003-10-09

    申请号：PCT/US2003/001851

    申请日：2003-01-21

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： KAMAL, Tazrien ,  NGO, Minh, Van ,  RAMSBEY, Mark, T. ,  SHIELDS, Jeffrey, A. ,  YANG, Jean, Y. ,  LINGUNIS, Emmanuil ,  SHIRAIWA, Hidehiko ,  HUI, Angela, T.

    IPC: H01L21/28

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines (525) (526) formed by using the hard mask extensions (524). A charge-trapping dielectric material (504) is deposited over a semiconductor substrate (501) and first and second bitlines (512) are formed therein. A wordline material (515) and a hard mask material (515) are deposited over the wordline material (515). A photoresist material (518) is deposited over the hard mask material (515) and is processed to form a patterned photoresist material (518). The hard mask material (515) is processed using the patterned photoresist material (518) to form a patterned hard mask material (519). The patterned photoresist is then removed. A hard mask extension material (524) is deposited over the wordline material (515) and is processed to form a hard mask extension (524). The wordline material (515) is processed using the patterned hard mask material (519) and the hard mask extension (524) to form a wordline (525), and the patterned hard mask material (519) and the hard mask extension (524) are then removed.

    Abstract translation: 提供一种用于通过使用硬掩模延伸部（524）形成的具有紧密间隔的字线（525）（526）的集成电路存储器的制造方法。 电荷俘获电介质材料（504）沉积在半导体衬底（501）上，并且在其中形成第一和第二位线（512）。 字线材料（515）和硬掩模材料（515）沉积在字线材料（515）上。 光致抗蚀剂材料（518）沉积在硬掩模材料（515）上并被处理以形成图案化的光致抗蚀剂材料（518）。 使用图案化的光致抗蚀剂材料（518）处理硬掩模材料（515）以形成图案化的硬掩模材料（519）。 然后去除图案化的光致抗蚀剂。 硬掩模延伸材料（524）沉积在字线材料（515）上并被处理以形成硬掩模延伸部（524）。 使用图案化的硬掩模材料（519）和硬掩模延伸部（524）来加工字线材料（515）以形成字线（525），并且图案化的硬掩模材料（519）和硬掩模延伸部（524） 然后被删除。

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