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    AN SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE
    3.
    发明申请
    AN SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE 审中-公开
    具有过程容限配置的基板二极管的SOI器件和形成SOI器件的方法

    公开(公告)号：WO2008094666A2

    公开(公告)日：2008-08-07

    申请号：PCT/US2008/001310

    申请日：2008-01-31

    Applicant: ADVANCED MICRO DEVICES, INC. ,  GEHRING, Andreas ,  HOENTSCHEL, Jan ,  WEI, Andy

    Inventor： GEHRING, Andreas ,  HOENTSCHEL, Jan ,  WEI, Andy

    IPC: H01L21/84 ,  H01L27/12

    CPC classification number: H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

    Abstract: A substrate diode for an SOI device (200, 300) is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings (21 IA, 21 IB, 31 IA, 311B) for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure (236, 336) used for defining the drain and source regions (237, 337), thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers (236, 336) in the transistor devices (230A, 230B, 330A, 33OB). In a further aspect, in addition to or alternatively, an offset spacer (360S) may be formed substantially without affecting the configuration of respective transistor devices (230A, 230B, 330A, 33OB).

    Abstract translation: 根据适当设计的制造流程形成用于SOI器件（200,300）的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面中，用于衬底二极管的相应开口（21A，21B，31A，311B）可以在形成用于限定漏极和源极区域（237,213）的对应侧壁间隔结构（236,336）之后形成， 337），从而获得二极管区域中的掺杂剂的显着的横向分布，其因此可以在随后的硅化步骤期间提供足够的工艺余量，其基础是去除晶体管器件（230A，230B）中的间隔物（236,336） 230B，330A，33OB）。 在另一方面，除了或者可选地，可以基本上不形成相应的晶体管器件（230A，230B，330A，33B）的配置来形成偏移间隔物（360S）。

    COMPENSATION OF DEGRADATION OF PERFORMANCE OF SEMICONDUCTOR DEVICES BY CLOCK DUTY CYCLE ADAPTATION
    5.
    发明申请
    COMPENSATION OF DEGRADATION OF PERFORMANCE OF SEMICONDUCTOR DEVICES BY CLOCK DUTY CYCLE ADAPTATION 审中-公开
    通过时钟周期适应性对半导体器件性能的降低的补偿

    公开(公告)号：WO2010060638A1

    公开(公告)日：2010-06-03

    申请号：PCT/EP2009/008470

    申请日：2009-11-27

    Applicant: ADVANCED MICRO DEVICES, INC ,  AMD FAB 36 LLIMITED LIABILITY COMPANY & CO. KG ,  PAPAGEORGIOU, Vassilios ,  WIATR, Maciej ,  HOENTSCHEL, Jan

    Inventor： PAPAGEORGIOU, Vassilios ,  WIATR, Maciej ,  HOENTSCHEL, Jan

    IPC: G06F11/00 ,  G01R31/317 ,  H01L23/34

    CPC classification number: G06F11/008

    Abstract: The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may efficiently be controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required.

    Abstract translation: 可以通过适当调整时钟信号的占空比来补偿集成电路的器件劣化。 为此，可以建立集成电路的占空比和整体性能特性之间的相关性，并且可以在设备的正常现场操作期间使用以改变占空比。 因此，可以实现有效的控制策略，因为可以有效地控制占空比，同时可能不需要时钟信号频率的改变和/或电源电压的增加。

    DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY PROVIDING EMBEDDED STRAIN INDUCING SEMICONDUCTOR MATERIAL IN THE ACTIVE REGION
    6.
    发明申请
    DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY PROVIDING EMBEDDED STRAIN INDUCING SEMICONDUCTOR MATERIAL IN THE ACTIVE REGION 审中-公开
    通过在主动区域中本地提供嵌入式应变诱导半导体材料在同一活动区域中形成的晶体管的驱动电流调整

    公开(公告)号：WO2010022971A1

    公开(公告)日：2010-03-04

    申请号：PCT/EP2009/006259

    申请日：2009-08-28

    Applicant: ADVANCED MICRO DEVICES, INC. ,  GRIEBENOW, Uwe ,  HOENTSCHEL, Jan

    Inventor： GRIEBENOW, Uwe ,  HOENTSCHEL, Jan

    IPC: H01L21/8234 ,  H01L21/8244

    CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  Y02P80/30

    Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing for a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used so as to adjust the ratio of the drive currents for the pull-down and pass transistors.

    Abstract translation: 可以基于通过在有源区域中提供至少一个嵌入式半导体合金而获得的不同应变水平来调整形成在公共有源区域中的下拉晶体管和传输晶体管的驱动电流能力，从而提供简化的总体 活动区域的几何配置。 因此，可以基于具有有源区域的简化配置的最小信道长度形成静态RAM单元，从而避免了在复杂器件中可观察到的显着的损耗损耗，其中常规地使用晶体管宽度的明显变化 以调节下拉和通过晶体管的驱动电流的比率。

    A TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY
    10.
    发明申请
    A TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY 审中-公开
    具有嵌入式SI / GE材料的晶体管，具有增强的跨基板均匀性

    公开(公告)号：WO2010037522A1

    公开(公告)日：2010-04-08

    申请号：PCT/EP2009/007001

    申请日：2009-09-29

    Applicant: ADVANCED MICRO DEVICES, INC. ,  MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SCOTT, Casey

    Inventor： MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SCOTT, Casey

    IPC: H01L21/336 ,  H01L29/04 ,  H01L29/78 ,  H01L21/8238

    CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

    Abstract: In sophisticated semiconductor devices a strain inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behaviour with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behaviour, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide for the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

    Abstract translation: 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以具有相对于不同晶体取向的各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而实现极薄的蚀刻停止层，其另外提供进一步减少来自通道的偏移的可能性 区域，而不会不利地导致整体过程变化。

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