公开(公告)号：JP2006278999A

公开(公告)日：2006-10-12

申请号：JP2005100248

申请日：2005-03-30

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KURACHI SHUNSUKE ,  KOMATANI TSUTOMU

IPC: H01L21/205 ,  C30B29/38 ,  H01L21/02 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812 ,  H01S5/183 ,  H01S5/343

CPC classification number: H01L21/3185 ,  B82Y20/00 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/3143 ,  H01L21/31604 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2924/0002 ,  H01S5/0201 ,  H01S5/0207 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/34333 ,  H01S2301/173 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate in which occurrence of warp and crack can be suppressed effectively and stripping of each surface of a semiconductor layer can be prevented, and to provide a substrate for growing semiconductor crystal, a semiconductor device, an optical semiconductor device, and their manufacturing processes.
SOLUTION: The semiconductor substrate (100) comprises a semiconductor crystal layer (2) grown on one surface of a substrate (1), and a stress relax layer (3) formed on the other surface and the side face of the substrate (1) and imparting a stress to the substrate (1) in the same direction as that of a stress being imparted to the substrate (1) by the semiconductor crystal layer (2). Since the stress being imparted to the substrate (1) by the semiconductor crystal layer (2) is offset, occurrence of warp and crack in the semiconductor substrate (100) is suppressed.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供可以有效地抑制发生翘曲和裂纹的半导体衬底，并且可以防止半导体层的每个表面的剥离，并且提供用于生长半导体晶体的衬底，半导体器件 ，光学半导体器件及其制造工艺。 解决方案：半导体衬底（100）包括在衬底（1）的一个表面上生长的半导体晶体层（2）和形成在衬底的另一个表面上的应力弛豫层（3） （1）并且通过半导体晶体层（2）以与施加到基板（1）的应力相同的方向向基板（1）施加应力。 由于通过半导体晶体层（2）赋予衬底（1）的应力偏移，所以抑制了半导体衬底（100）中的翘曲和裂纹的发生。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006261252A

公开(公告)日：2006-09-28

申请号：JP2005074103

申请日：2005-03-15

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KURACHI SHUNSUKE ,  KOMATANI TSUTOMU

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01S5/183

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device for enabling high output operation by reducing a collapse phenomenon without the separation of an insulating layer from a semiconductor layer.
SOLUTION: The semiconductor device comprises a GaN system semiconductor layer 11 formed on a substrate 10, and a silicon nitride film layer formed on the GaN system semiconductor layer to have a silicon/nitrogen composition ratio of 0.8 to 2.5 or an aluminum nitride film layer 20 having an aluminum/silicon composition ratio of 1.0 to 2.5. The manufacturing method of the semiconductor device can improve close contact between the insulating layer and the semiconductor layer by selecting a composition of the silicon nitride layer formed on the semiconductor layer, prevent the separation of the insulating film layer from the surface of semiconductor layer, and reduce the collapse phenomenon.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高可靠性的半导体器件，用于通过减少崩溃现象而实现高输出操作，而不会使绝缘层与半导体层分离。 解决方案：半导体器件包括形成在衬底10上的GaN系半导体层11和形成在GaN系半导体层上以使硅/氮组成比为0.8至2.5的氮化硅膜层或氮化铝 铝/硅组成比为1.0〜2.5的薄膜层20。 半导体器件的制造方法可以通过选择形成在半导体层上的氮化硅层的组成，防止绝缘膜层与半导体层的表面分离来提高绝缘层与半导体层之间的紧密接触，以及 减少崩溃现象。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005322811A

公开(公告)日：2005-11-17

申请号：JP2004140431

申请日：2004-05-10

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KOMATANI TSUTOMU

IPC: H01L21/28 ,  H01L21/00 ,  H01L21/033 ,  H01L21/04 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/338 ,  H01L21/461 ,  H01L21/768 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0475 ,  H01L21/3081

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing GaN based semiconductor devices for high precision processes, by improving the adhesion of mask for dry etching to the surface of etching material.
SOLUTION: A Ti film 22 and an Ni film 24 are laminated, in this order, on a GaN-based semiconductor layer of etching material and a substrate 21 of SiC or sapphire, for film formation by vacuum deposition. The laminated film is patterned by photolithographic method to form a mask. If the etching base body is, for example, the SiC substrate, the thermal expansion coefficient of SiC is 4.2×10
-6 /°C and that of Ni is 12.8×10
-6 /°C. By providing the Ti film 22, whose thermal expansion coefficient is 9.0×10
-6 /°C, the distortion generated by thermal expansion due to the rise of the temperature during etching is reduced to improve adhesion of the mask to the SiC substrate surface, resulting in suppressing of the occurrence of peeling or cracking.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于高精度工艺的GaN基半导体器件的方法，通过改善用于干蚀刻的掩模与蚀刻材料的表面的粘附。 解决方案：依次将Ti膜22和Ni膜24层叠在蚀刻材料的GaN基半导体层和SiC或蓝宝石的衬底21上，用于通过真空沉积成膜。 通过光刻法将层压膜图案化以形成掩模。 如果蚀刻基体是例如SiC基板，则SiC的热膨胀系数为4.2×10 -6 /℃，Ni的热膨胀系数为12.8×10 -6 < / SP> /℃。 通过设置其热膨胀系数为9.0×10 -6 /℃的Ti膜22，由于蚀刻期间的温度上升而由热膨胀产生的变形减小，以提高 掩模到SiC衬底表面，导致抑制剥离或开裂的发生。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2008306027A

公开(公告)日：2008-12-18

申请号：JP2007152496

申请日：2007-06-08

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： NISHI SHINKO ,  IKUMATSU HITOSHI ,  KOMATANI TSUTOMU

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872

Abstract: PROBLEM TO BE SOLVED: To improve coating characteristics of an electrode formed in the opening of an insulating film.
SOLUTION: The manufacturing method of a semiconductor device includes a process for forming a first insulating film 20 on a compound semiconductor layer 16, a process for thermally treating the first insulating film 20, a process for forming a second insulating film 22 on the first insulating film 20, a process for forming openings 44 and 46 through which the compound semiconductor layer 16 is exposed by selectively etching the second insulating film 22 and the first insulating film 20 using the same mask 40, and a process for forming an electrode that contacts to the inner wall of the openings 44 and 46.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：改善在绝缘膜的开口中形成的电极的涂层特性。 解决方案：半导体器件的制造方法包括在化合物半导体层16上形成第一绝缘膜20的工艺，第一绝缘膜20的热处理工艺，第二绝缘膜22的形成工艺 第一绝缘膜20，通过使用相同的掩模40选择性地蚀刻第二绝缘膜22和第一绝缘膜20来形成开口44和46的方法，化合物半导体层16通过其暴露，以及用于形成电极的工艺 接触到开口44和46的内壁。版权所有：（C）2009，JPO＆INPIT

公开(公告)号：JP2005286135A

公开(公告)日：2005-10-13

申请号：JP2004098599

申请日：2004-03-30

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： TANAKA MASAKIMI ,  KOMATANI TSUTOMU

IPC: H01L21/318 ,  H01L21/338 ,  H01L21/8242 ,  H01L29/20 ,  H01L29/51 ,  H01L29/778 ,  H01L29/812 ,  H01L33/06 ,  H01L33/32 ,  H01L33/44 ,  H01L33/00

CPC classification number: H01L29/51 ,  H01L29/2003 ,  H01L29/7787

Abstract: PROBLEM TO BE SOLVED: To provide a nitride semiconductor device wherein a gate leakage current and current collapse are suppressed to a level for satisfying the high characteristic requirement of a commercial level, and to provide a manufacturing method. SOLUTION: The surface of an n-type GaN thin film layer 140 is passivated by providing a source 150, a gate 160, and a drain 170 for bias application onto the n-type GaN thin film layer 140 apart from each other, and by providing a SiN protection film 180 whose hydrogen content is 15% or below to the surface of the n-type GaN thin film layer 140 exposed between the source 150 and the gate 160, and between the gate 160 and the drain 170. Thus, a state change on the surface of the nitride semiconductor and a change in a charging state of the surface defect level caused by the presence of hydrogen in the SiN protection film 180 are suppressed so that the gate leakage current and current collapse can be suppressed to a level for satisfying the high characteristic requirement of the commercial level. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种氮化物半导体器件，其中栅极漏电流和电流崩溃被抑制到满足商业级的高特性要求的水平，并提供制造方法。 解决方案：通过提供源极150，栅极160和漏极170来钝化n型GaN薄膜层140的表面，以将偏压施加到相互间隔开的n型GaN薄膜层140上 并且通过在源极150和栅极160之间以及在栅极160和漏极170之间设置暴露于n型GaN薄膜层140的表面的氢含量为15％或更低的SiN保护膜180。 因此，抑制氮化物半导体的表面的状态变化和由SiN保护膜180中的氢存在引起的表面缺陷水平的充电状态的变化，从而可以抑制栅极漏电流和电流塌陷 达到满足商业层面高特点要求的水平。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2009200306A

公开(公告)日：2009-09-03

申请号：JP2008041345

申请日：2008-02-22

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KOMATANI TSUTOMU

IPC: H01L21/338 ,  H01L21/318 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L21/3185 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66863 ,  H01L29/7787

Abstract: PROBLEM TO BE SOLVED: To suppress an unstable phenomenon caused by a silicon-rich silicon nitride film. SOLUTION: This manufacturing method of a semiconductor device includes processes of: forming a first silicon nitride film 12 having a refractive index of 2.2 or more on a semiconductor layer 11 formed of a GaN-based or InP-based compound semiconductor; forming a second silicon nitride film 14 having a lower refractive index than the first silicon nitride film 12 on the first silicon nitride film 12; forming a source electrode 16 and a drain electrode 18 in regions with the semiconductor layer 11 exposed therefrom; heat-treating the source electrode 16 and drain electrode 18 with the first silicon nitride film 12 and the second silicon nitride film 14 formed; and forming a gate electrode on the semiconductor layer 11 between the source electrode 16 and the drain electrode 18. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：抑制由富硅氮化硅膜引起的不稳定现象。 解决方案：这种半导体器件的制造方法包括以下工序：在由GaN基或InP系化合物半导体形成的半导体层11上形成折射率为2.2以上的第一氮化硅膜12; 在第一氮化硅膜12上形成折射率低于第一氮化硅膜12的第二氮化硅膜14; 在半导体层11露出的区域内形成源电极16和漏电极18; 用形成的第一氮化硅膜12和第二氮化硅膜14对源电极16和漏电极18进行热处理; 并且在源电极16和漏电极18之间的半导体层11上形成栅极电极。（C）2009，JPO＆INPIT

公开(公告)号：JP2008306026A

公开(公告)日：2008-12-18

申请号：JP2007152495

申请日：2007-06-08

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： IKUMATSU HITOSHI ,  NISHI SHINKO ,  KOMATANI TSUTOMU

IPC: H01L21/28 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To suppress current collapse and peeling and floating of an insulating film.
SOLUTION: The method of manufacturing a semiconductor device performs heat treatment for forming ohmic electrodes 17 and 18 on a GaN semiconductor layer 16. The heat treatment is performed while the side walls of the ohmic electrodes 17 and 18 are away from a side wall of an insulating film 24 provided on the GaN semiconductor layer 16. The invention suppresses current collapse and peeling and floating of the insulating film.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：抑制绝缘膜的电流塌陷和剥离和漂浮。 解决方案：制造半导体器件的方法在GaN半导体层16上进行用于形成欧姆电极17和18的热处理。在欧姆电极17和18的侧壁远离一侧进行热处理 设置在GaN半导体层16上的绝缘膜24的壁。本发明抑制绝缘膜的电流塌陷和剥离和浮动。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008306025A

公开(公告)日：2008-12-18

申请号：JP2007152494

申请日：2007-06-08

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KOMATANI TSUTOMU ,  NISHI SHINKO ,  IKUMATSU HITOSHI

IPC: H01L21/338 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To effectively reduce current collapse even when a silicon nitride film having a low refractive index is used. SOLUTION: The present invention relates to a manufacturing method of a semiconductor device including the stages of: forming a silicon nitride film 18 of ≥2.1 to COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：即使使用具有低折射率的氮化硅膜，也能有效地减少电流崩塌。 解决方案：本发明涉及一种半导体器件的制造方法，包括以下阶段：在GaN基半导体层16上形成折射率≥2.1至<2.2的氮化硅膜18; 在氮化硅膜18的开口中形成欧姆电极20和22; 并且对欧姆电极20和22进行热处理。在本发明中，通过在形成折射率≥2.1的氮化硅膜18的状态下对欧姆电极进行热处理，可以防止电流崩溃。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006278812A

公开(公告)日：2006-10-12

申请号：JP2005096902

申请日：2005-03-30

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KURACHI SHUNSUKE ,  KOMATANI TSUTOMU

IPC: H01L21/338 ,  H01L21/205 ,  H01L21/28 ,  H01L21/318 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can perform high output operation by suppressing collapse phenomenon occurring when a high drain voltage is applied, and to provide its fabrication process, a substrate for manufacturing that semiconductor device, and its production process.
SOLUTION: The semiconductor device comprises a GaN based semiconductor layer (13) formed on a substrate (11), an insulating film (25) composed of silicon nitride, silicon oxide, silicon oxide nitride, aluminium nitride or aluminium oxide containing silicon or aluminium more than stoichiometric composition ratio formed on the surface of the GaN based semiconductor layer (13), a gate electrode (18) formed on the GaN based semiconductor layer (13), and a source electrode (14) and a drain electrode (16) formed to hold the gate electrode (18) between. A process for fabricating that semiconductor device, a substrate for manufacturing that semiconductor device, and its production process are also provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体器件，其可以通过抑制施加高漏极电压时发生的塌陷现象而进行高输出操作，并提供其制造工艺，用于制造该半导体器件的基板及其制造 处理。 解决方案：半导体器件包括形成在衬底（11）上的GaN基半导体层（13），由氮化硅，氧化硅，氧化硅氮化物，氮化铝或含氧化硅的硅构成的绝缘膜（25） 或在GaN基半导体层（13）的表面上形成的比化学计量组成比高的铝，形成在GaN基半导体层（13）上的栅电极（18），以及源电极（14）和漏电极 16），其形成为将栅电极（18）保持在其间。 还提供了制造该半导体器件的工艺，用于制造该半导体器件的衬底及其制造工艺。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2008098456A

公开(公告)日：2008-04-24

申请号：JP2006279351

申请日：2006-10-13

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KOSAKA TOSHIYUKI ,  KOMATANI TSUTOMU

IPC: H01L21/3065 ,  H01L21/3205 ,  H01L23/52

CPC classification number: H01L21/0445 ,  H01L21/0332 ,  H01L21/76898

Abstract: PROBLEM TO BE SOLVED: To suppress warping, breaking, cracking, or the like of a substrate which is caused by a difference in thermal expansion factors between the substrate and a metal mask.
SOLUTION: The manufacturing method of a semiconductor device includes a process for forming a metal mask comprising a first trimming pattern (30) for opening a wanted region and a second trimming pattern (32) for opening such region as separates the material of metal mask into a plurality of sections that are not connected each other, and a process for selectively removing at least either a substrate or a layer provided on the substrate by dry-etching using the metal mask.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：抑制由基板和金属掩模之间的热膨胀因子的差异引起的基板的翘曲，断裂或开裂等。 解决方案：半导体器件的制造方法包括用于形成金属掩模的工艺，该金属掩模包括用于打开所需区域的第一修整图案（30）和用于打开所述区域的第二修整图案（32） 金属掩模形成彼此不连接的多个部分，以及通过使用金属掩模的干法蚀刻来选择性地去除设置在基板上的基板或层中的至少一个的工艺。 版权所有（C）2008，JPO＆INPIT