2.
    发明专利
    未知

    公开(公告)号:DE69129952T2

    公开(公告)日:1999-02-11

    申请号:DE69129952

    申请日:1991-03-19

    Applicant: FUJITSU LTD

    Abstract: In a network, a route which can be uniquely identified is constructed by selecting an arbitrary packet-switching node and an arbitrary transmission line in an arbitrary order from the network. A route memory unit (301) stores data indicating which route is involved in which transmission line within the network. A congested state detecting unit (302) detects a congested state of a transmission line accommodated within its own node. The detected congested state is transmitted to another node by a congested state informing unit (303) as congested state information. A route identifying unit (304) receives the congested state information from the other node and retrieves a route within a corresponding transmission line from the route memory unit (301) to thereby identify the route accommodated within its node. A route control unit (305) carries out control of the congested state of the identified route on the basis of the received congested state information. As described above, since traffic passing the transmission line is classified into "route" and grouped, an object whose congestion is to be supervised is limited and each node can regulated only the traffic passing the transmission line in which the congestion occurred in units of routes.

    3.
    发明专利
    未知

    公开(公告)号:DE69129952D1

    公开(公告)日:1998-09-17

    申请号:DE69129952

    申请日:1991-03-19

    Applicant: FUJITSU LTD

    Abstract: In a network, a route which can be uniquely identified is constructed by selecting an arbitrary packet-switching node and an arbitrary transmission line in an arbitrary order from the network. A route memory unit (301) stores data indicating which route is involved in which transmission line within the network. A congested state detecting unit (302) detects a congested state of a transmission line accommodated within its own node. The detected congested state is transmitted to another node by a congested state informing unit (303) as congested state information. A route identifying unit (304) receives the congested state information from the other node and retrieves a route within a corresponding transmission line from the route memory unit (301) to thereby identify the route accommodated within its node. A route control unit (305) carries out control of the congested state of the identified route on the basis of the received congested state information. As described above, since traffic passing the transmission line is classified into "route" and grouped, an object whose congestion is to be supervised is limited and each node can regulated only the traffic passing the transmission line in which the congestion occurred in units of routes.

    DATA TRANSFER SYSTEM HAVING TRANSFER DISCRIMINATION CIRCUIT

    公开(公告)号:AU596459B2

    公开(公告)日:1990-05-03

    申请号:AU8100287

    申请日:1987-10-16

    Applicant: FUJITSU LTD

    Abstract: A data transfer system having a transfer discrimination circuit for discriminating the type of data transfer between an input/output channel device and I/O devices for a computer includes a transfer discrimination circuit. This circuit includes a edge detection unit operating in response to a tag signal supplied to the edge detection unit for detecting the trailing edge of the tag signal after a leading edge of the tag signal has passed. The edge detection unit having a leading edge detector, a trailing edge detector, a storage element, and logic gate circuits. A timing unit is included operating in response to the output of the edge detection unit for counting a predetermined time, along with a discrimination storage unit operating in response to the output of the timing unit for delivering an output indicating an interlock data transfer or an output indicating a data streaming feature data transfer.

    LOOP TRANSMISSION SYSTEM AND METHOD OF CONTROLLING ITS LOOP-BACK CONDITION

    公开(公告)号:DE3377609D1

    公开(公告)日:1988-09-08

    申请号:DE3377609

    申请日:1983-08-18

    Applicant: FUJITSU LTD

    Abstract: @ A loop transmission system comprises a plurality of node stations (ND-A...ND-D), a supervisory station (SV), and two duplicate loop transmission lines (TL1, TL2) which transmit signals in opposite directions. In operation of the system, the supervisory station sends out loop-back commands (LB-0 ON, LB-1 ON) via both of the duplicate loop transmission lines when faults are detected on both of the transmission lines at the same time. Upon receipt of a loop-back command, each of the node stations establishes a loop-back path (TLC) while retaining a connection path to a succeeding note station. The supervisory station then sends release commands (LB-0 OFF, LB-1 OFF) to the node stations, and the loop-back path is released only in those node stations which receive signals normally from both of the duplicate loop transmission lines.

    6.
    发明专利
    未知

    公开(公告)号:BR8304681A

    公开(公告)日:1984-04-10

    申请号:BR8304681

    申请日:1983-08-29

    Applicant: FUJITSU LTD

    Abstract: @ A loop transmission system comprises a plurality of node stations (ND-A...ND-D), a supervisory station (SV), and two duplicate loop transmission lines (TL1, TL2) which transmit signals in opposite directions. In operation of the system, the supervisory station sends out loop-back commands (LB-0 ON, LB-1 ON) via both of the duplicate loop transmission lines when faults are detected on both of the transmission lines at the same time. Upon receipt of a loop-back command, each of the node stations establishes a loop-back path (TLC) while retaining a connection path to a succeeding note station. The supervisory station then sends release commands (LB-0 OFF, LB-1 OFF) to the node stations, and the loop-back path is released only in those node stations which receive signals normally from both of the duplicate loop transmission lines.

    PACKET SWITCHING SYSTEM HAVING BUS MATRIX SWITCH

    公开(公告)号:CA2015514C

    公开(公告)日:1996-08-06

    申请号:CA2015514

    申请日:1990-04-26

    Applicant: FUJITSU LTD

    Abstract: A packet switching system having a matrix switch including input packet transfer buses and output packet transfer buses. Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.

    8.
    发明专利
    未知

    公开(公告)号:DE3788721D1

    公开(公告)日:1994-02-17

    申请号:DE3788721

    申请日:1987-10-16

    Applicant: FUJITSU LTD

    Abstract: A data transfer system having a transfer discrimination circuit for discriminating the type of data transfer between an input/output channel device and I/O devices for a computer includes a transfer discrimination circuit. This circuit includes a edge detection unit operating in response to a tag signal supplied to the edge detection unit for detecting the trailing edge of the tag signal after a leading edge of the tag signal has passed. The edge detection unit having a leading edge detector, a trailing edge detector, a storage element, and logic gate circuits. A timing unit is included operating in response to the output of the edge detection unit for counting a predetermined time, along with a discrimination storage unit operating in response to the output of the timing unit for delivering an output indicating an interlock data transfer or an output indicating a data streaming feature data transfer.

    9.
    发明专利
    未知

    公开(公告)号:DE69032699T2

    公开(公告)日:1999-04-15

    申请号:DE69032699

    申请日:1990-04-27

    Applicant: FUJITSU LTD

    Abstract: A packet switching system having a matrix switch including input packet transfer buses (61 - 6n) and output packet transfer buses (81 - 8n). Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.

    ROUTE REGULATING APPARATUS
    10.
    发明专利

    公开(公告)号:CA2038458A1

    公开(公告)日:1991-09-20

    申请号:CA2038458

    申请日:1991-03-18

    Applicant: FUJITSU LTD

    Abstract: In a network, a route which can be uniquely identified is constructed by selecting an arbitrary packet-switching node and an arbitrary transmission line in an arbitrary order from the network. A route memory unit (301) stores data indicating which route is involved in which transmission line within the network. A congested state detecting unit (302) detects a congested state of a transmission line accommodated within its own node. The detected congested state is transmitted to another node by a congested state informing unit (303) as congested state information. A route identifying unit (304) receives the congested state information from the other node and retrieves a route within a corresponding transmission line from the route memory unit (301) to thereby identify the route accommodated within its node. A route control unit (305) carries out control of the congested state of the identified route on the basis of the received congested state information. As described above, since traffic passing the transmission line is classified into "route" and grouped, an object whose congestion is to be supervised is limited and each node can regulated only the traffic passing the transmission line in which the congestion occurred in units of routes.

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