中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

115 records (took 0.027 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE69226742D1

    公开(公告)日：1998-10-01

    申请号：DE69226742

    申请日：1992-09-21

    Applicant: FUJITSU LTD

    Inventor： OGAWA JUNJI ,  TAKITA MASATO

    IPC: H01L21/82 ,  H01L21/822 ,  H01L23/495 ,  H01L23/50 ,  H01L27/04

    Abstract: A semiconductor comprises an LOC structure. A bonding pad (24) solely for receiving a signal is formed parallel to a perimeter on top in the middle of the said element-formation surface, a bonding pad (25) solely for transmitting a signal is formed around the periphery of the said element-formation surface, an inner lead (26) solely for receiving a signal has its tip positioned parallel to the perimeter on top in the middle of the said element-formation surface, an inner lead (27) solely for transmitting a signal has its tip positioned on top of the periphery of the said element-formation surface.

    2.
    发明专利
    未知

    公开(公告)号：DE3685678D1

    公开(公告)日：1992-07-23

    申请号：DE3685678

    申请日：1986-04-10

    Applicant: FUJITSU LTD

    Inventor： OGAWA JUNJI

    IPC: G11C7/00 ,  G06F12/02 ,  G06F12/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/40 ,  G11C11/401 ,  G11C11/41 ,  G11C8/00

    Abstract: A video random access memory (Video RAM) comprises a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially accessed, each RAM and corresponding shift register being connected by transfer gates (8) in orderto transfer read/write data. Ther Video RAM further comprises an input/output circuit (4) which is operatively connected to the shift registers and is switched from an input side to an output side, or from an output side to an input side, in response to the direction of data transfer between the RAM and the shift register, and a transfer control circuit (5) for controlling the switching of the input/output circuit and for controlling the direction of data transfer, based on predetermined modes of the input signals.

    3.
    发明专利
    未知

    公开(公告)号：DE3578254D1

    公开(公告)日：1990-07-19

    申请号：DE3578254

    申请日：1985-10-16

    Applicant: FUJITSU LTD

    Inventor： OGAWA JUNJI

    IPC: G11C7/00 ,  G11C7/10 ,  G11C11/40 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/41 ,  G11C8/00

    Abstract: An identification system to identify objects from a remote interrogation station is used with moving objects such as railroad cars. The system remotely programs and stores information on an object and remotely retrieves information from the object. An information and identity storage device (10) is located on the object and at least one interrogation station (11) is located remotely from the object.

    SEMICONDUCTOR MEMORY DEVICE HAVING SERIAL DATA INPUT AND OUTPUT CIRCUIT
    4.
    发明专利
    SEMICONDUCTOR MEMORY DEVICE HAVING SERIAL DATA INPUT AND OUTPUT CIRCUIT 未知

    公开(公告)号：CA1246741A

    公开(公告)日：1988-12-13

    申请号：CA498754

    申请日：1985-12-30

    Applicant: FUJITSU LTD ,  FUJITSU VLSI LTD

    Inventor： NOGUCHI MASAAKI ,  OGAWA JUNJI ,  TAKEMAE YOSHIHIRO

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

    Abstract: SEMICONDUCTOR MEMORY DEVICE HAVING SERIAL DATA INPUT AND OUTPUT CIRCUIT A dual-port type semiconductor memory device having a serial data input and output circuit provided outside of a memory cell array and operable for high-speed serial data input and output of data in addition to random data access. The semiconductor memory device includes a single decoding circuit triggering at least one gate for transferring data to be stored into or read from the memory cell array in a random data access mode and setting a single bit into a corresponding shift register in the serial data input and output circuit in a serial data input and output operation mode. Preferably, the decoding circuit is operated only during a time for operatively connecting bit lines and latch circuits in the serial data input and output circuit in the serial data input and output operation mode. The serial data input and output circuit is operable independently from the memory cell array, except during the time for operatively connecting the bit lines and the latch circuits through transfer gates, for serially inputting data to or outputting data from the latch circuits through serial data bus by sequentially triggering the serial gates from a certain gate designated by the corresponding shift register in response to the decoding circuit.

    Signalübertragungssystem zur Übertragung von Signalen zwischen LSI-Chips
    5.
    发明专利
    Signalübertragungssystem zur Übertragung von Signalen zwischen LSI-Chips 未知

    公开(公告)号：DE19744620B4

    公开(公告)日：2014-05-22

    申请号：DE19744620

    申请日：1997-10-09

    Applicant: FUJITSU LTD

    Inventor： TAMURA HIROTAKA ,  SAITO MIYOSHI ,  GOTOH KOHTAROH ,  WAKAYAMA SHIGETOSHI ,  OGAWA JUNJI ,  ARAKI HISAKATSU ,  CHEUNG TSZ-SHING

    IPC: G06F3/00 ,  G06F13/40 ,  G06F1/10 ,  G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

    Abstract: Signalübertragungssystem zur Übertragung von digitalen Signalen mit – mindestens einer Übertragungsleitung, – einem Sender (61, 63) zum Senden von Zeichen; – und einem Empfänger (62) zum Empfangen der gesendeten Zeichen, bei dem zur Verringerung des Energieverbrauchs: – ein Abschlußwiderstand (3, 4) an einem oder beiden Enden der Signalübertragungsleitung (2) vorgesehen ist, der auf einen Wert größer als eine charakteristische Impedanz der Signalübertragungsleitung (2) gesetzt ist und/oder – zumindest ein Widerstand (7) in Reihe mit der Signalübertragungsleitung (2) vorgesehen ist, – sodass die inhärente Antwortzeit, mit der ein Spannungssignal eines Zeichens auf der Übertragungsleitung (2) bei einer Übertragung längs der Übertragungsleitung (2) antwortet, ungefähr gleich oder größer als die Länge eines übertragenen Zeichen wird, – wobei eine Bestimmungseinheit (42) zur Vorhersage der Intersymbol-Interferenz aus vorherig empfangenen Signalen verwendet wird, um eine Partialantwort der Übertragungsleitung durch Subtrahieren des vorhergesagten Intersymbol-Interferenzwerts aus einer gegenwärtig empfangenen Signalspannung zu erfassen.

    8.
    发明专利
    未知

    公开(公告)号：DE69226742T2

    公开(公告)日：1999-01-14

    申请号：DE69226742

    申请日：1992-09-21

    Applicant: FUJITSU LTD

    Inventor： OGAWA JUNJI ,  TAKITA MASATO

    IPC: H01L21/82 ,  H01L21/822 ,  H01L23/495 ,  H01L23/50 ,  H01L27/04

    Abstract: A semiconductor comprises an LOC structure. A bonding pad (24) solely for receiving a signal is formed parallel to a perimeter on top in the middle of the said element-formation surface, a bonding pad (25) solely for transmitting a signal is formed around the periphery of the said element-formation surface, an inner lead (26) solely for receiving a signal has its tip positioned parallel to the perimeter on top in the middle of the said element-formation surface, an inner lead (27) solely for transmitting a signal has its tip positioned on top of the periphery of the said element-formation surface.

    10.
    发明专利
    未知

    公开(公告)号：DE3685678T2

    公开(公告)日：1993-01-14

    申请号：DE3685678

    申请日：1986-04-10

    Applicant: FUJITSU LTD

    Inventor： OGAWA JUNJI

    IPC: G11C7/00 ,  G06F12/02 ,  G06F12/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/40 ,  G11C11/401 ,  G11C11/41 ,  G11C8/00

    Abstract: A video random access memory (Video RAM) comprises a plurality of RAM and shift register sets, each RAM (7) being randomly accessed and each shift register (3) being serially accessed, each RAM and corresponding shift register being connected by transfer gates (8) in orderto transfer read/write data. Ther Video RAM further comprises an input/output circuit (4) which is operatively connected to the shift registers and is switched from an input side to an output side, or from an output side to an input side, in response to the direction of data transfer between the RAM and the shift register, and a transfer control circuit (5) for controlling the switching of the input/output circuit and for controlling the direction of data transfer, based on predetermined modes of the input signals.

Patent Agency Ranking