公开(公告)号：DE69023819T2

公开(公告)日：1996-04-11

申请号：DE69023819

申请日：1990-05-30

Applicant: FUJITSU LTD ,  FUJITSU VLSI LTD

Inventor： MATSUKI HIROHISA ,  HARADA SHIGEKI ,  SUGIMOTO MASAHIRO ,  YOSHIDA TOSHIKI

IPC: H01L23/055 ,  H01L23/367 ,  H01L23/498 ,  H01L23/485 ,  H01L23/50

Abstract: A semiconductor device comprises a semiconductor chip (21), a substrate (22) for supporting the semiconductor chip, a plurality of terminals (29) provided on the substrate for external connections, a plurality of lead wires (25) provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure comprises at least a lower conductor layer (24) provided on the substrate and patterned into a plurality of pattern portions (41, 42) connected electrically to the terminals, an insulator layer (23) provided on the lower conductor layer, and an upper conductor layer (270) provided above the insulator layer. The upper conductor layer is formed with a connection area (26) immediately below the lead wires on the semiconductor chip when the semiconductor chip is mounted on the substrate, the upper conductor layer is patterned in the connection area into a plurality of conductor strips (27) extending parallel with each other in correspondence to the lead wires, the insulator layer is provided with contact holes (28) so as to connect electrically the conductor strips of the upper conductor layer with the pattern portions of the lower conductor layer. In the semiconductor device, each of the pattern portions in the connection area has an edge (41e, 42e) extending obliquely to the conductor strips of the upper conductor layer wherein the pattern portions are disposed so that a pair of adjacent pattern portions have respective edges opposing with each other and extending parallel with each other with a lateral gap (g) extending therebetween.

公开(公告)号：DE3880402T2

公开(公告)日：1993-07-29

申请号：DE3880402

申请日：1988-08-25

Applicant: FUJITSU LTD

Inventor： HARADA SHIGEKI ,  SUGIMOTO MASAHIRO

IPC: C23C14/06 ,  C04B41/51 ,  C04B41/52 ,  C04B41/89 ,  C23C14/14 ,  C23C14/18 ,  C23C14/58 ,  H01L23/10 ,  H05K1/03 ,  H05K3/38 ,  C04B41/90

Abstract: A metallization layer structure includes an intermediate layer (15) formed on an aluminum nitride ceramics base (11). The intermediate layer contains aluminum titanium nitride. A titanium layer (12) is formed on the intermediate layer. A heat-resistant metallic layer (13) is formed on the titanium layer. A metallic layer (14) for facilitating soldering or brazing is formed on the heat-resistant metallic layer.

公开(公告)号：DE3684128D1

公开(公告)日：1992-04-09

申请号：DE3684128

申请日：1986-12-22

Applicant: FUJITSU LTD

Inventor： WAKASUGI YASUMASA ,  SUGIMOTO MASAHIRO

IPC: C04B35/18 ,  C04B35/195 ,  H01B3/12 ,  H01L23/15 ,  H05K1/03 ,  H01L23/14

Abstract: A low dielectric constant ceramic plate comprised of 90 to 98% of mullite (3Al2O3.2SiO2) and 10 to 2% of a sintering promotor comprised of 0.5 to 3% of magnesia (MgO) and 1.5 to 7% of calcium oxide (CaO).

公开(公告)号：CA1246755A

公开(公告)日：1988-12-13

申请号：CA504584

申请日：1986-03-20

Applicant: FUJITSU LTD

Inventor： MIYAUCHI AKIRA ,  NISHIMOTO HIROSHI ,  OKIYAMA TADASHI ,  KITASAGAMI HIROO ,  SUGIMOTO MASAHIRO ,  TAMADA HARUO ,  EMORI SHINJI

IPC: H01L23/057 ,  H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34 ,  H01L27/00

Abstract: SEMICONDUCTOR DEVICE A semiconductor device provided with signal lines which connect a chip provided at a top portion of a package with external terminals provided at a bottom portion of the package. The signal lines have portions formed along side surfaces of the package. Ground surfaces are formed at predetermined distances on two sides of the high-speed signal lines. Coplaner waveguide is formed by the high-speed signal lines and the ground surfaces, so the impedance of vertical portions of the high-speed signal lines is matched to the circuits connected thereto.

公开(公告)号：CA1246170A

公开(公告)日：1988-12-06

申请号：CA506182

申请日：1986-04-09

Applicant: FUJITSU LTD

Inventor： MIYAUCHI AKIRA ,  NISHIMOTO HIROSHI ,  OKIYAMA TADASHI ,  KITASAGAMI HIROO ,  SUGIMOTO MASAHIRO ,  TAMADA HARUO ,  EMORI SHINJI

IPC: H01L23/02 ,  H01L23/04 ,  H01L23/12 ,  H01L23/50 ,  H01L23/64 ,  H01L23/66 ,  H01P3/08 ,  H01P5/02 ,  H01P5/08 ,  H05K1/02 ,  H05K3/32

Abstract: INTEGRATED CIRCUIT DEVICE HAVING STRIP LINE STRUCTURE THEREIN An integrated circuit device including: at least one semiconductor chip (3) having a plurality of circuit elements; a package (21 to 24) enclosing the semiconductor chip with a hermetic seal; and a strip line unit (15-2, 11-1b, 11-2, 20 and 23 : 15-1, 11-1, 11-2, 11-3, 12-1 and 20) for connecting the circuit elements in the semiconductor chip to circuit outside of the package. The stripline unit having a microstrip line structure and a triplate strip line structure serial-connected to the microstrip line structure and connecting the outside circuits. The triplate strip line structure has a characteristic impedance equal to that of the microstrip line structure so that the strip line unit satisfies the required impedance matching. A center of the conductive layer strip line of the triplate strip line structure has a smaller width than that of a microstrip line of the microstrip line structure to have a predetermined impedance so that the triplate strip line structure has a same characteristic impedance as that of the microstrip line structure.

公开(公告)号：DE69023819D1

公开(公告)日：1996-01-11

申请号：DE69023819

申请日：1990-05-30

Applicant: FUJITSU LTD ,  FUJITSU VLSI LTD

Inventor： MATSUKI HIROHISA ,  HARADA SHIGEKI ,  SUGIMOTO MASAHIRO ,  YOSHIDA TOSHIKI

IPC: H01L23/055 ,  H01L23/367 ,  H01L23/498 ,  H01L23/485 ,  H01L23/50

Abstract: A semiconductor device comprises a semiconductor chip (21), a substrate (22) for supporting the semiconductor chip, a plurality of terminals (29) provided on the substrate for external connections, a plurality of lead wires (25) provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure comprises at least a lower conductor layer (24) provided on the substrate and patterned into a plurality of pattern portions (41, 42) connected electrically to the terminals, an insulator layer (23) provided on the lower conductor layer, and an upper conductor layer (270) provided above the insulator layer. The upper conductor layer is formed with a connection area (26) immediately below the lead wires on the semiconductor chip when the semiconductor chip is mounted on the substrate, the upper conductor layer is patterned in the connection area into a plurality of conductor strips (27) extending parallel with each other in correspondence to the lead wires, the insulator layer is provided with contact holes (28) so as to connect electrically the conductor strips of the upper conductor layer with the pattern portions of the lower conductor layer. In the semiconductor device, each of the pattern portions in the connection area has an edge (41e, 42e) extending obliquely to the conductor strips of the upper conductor layer wherein the pattern portions are disposed so that a pair of adjacent pattern portions have respective edges opposing with each other and extending parallel with each other with a lateral gap (g) extending therebetween.

公开(公告)号：DE69018846T2

公开(公告)日：1995-08-24

申请号：DE69018846

申请日：1990-02-08

Applicant: FUJITSU LTD

Inventor： SHIMIZU NOBUTAKA ,  TSUJIMURA TAKEHISA ,  SUGIMOTO MASAHIRO ,  HARADA SHIGEKI

IPC: H01L23/04 ,  H01L23/057 ,  H01L23/367 ,  H01L23/498

Abstract: A ceramic package type semiconductor device (30, 50, 60, 70, 80) comprising: a ceramic substrate (32, 52, 72) having a wiring pattern layer (37, 57, 77) formed on a top surface thereof; at least one semiconductor element (31, 51a-51c, 71) mounted on the ceramic substrate with a top face thereof facing downward and electrically connected to the wiring pattern layer; a metal cap (33, 53, 73) having at least one through-hole (33c, 53c1-53c6, 73c) corresponding to an external size of the semiconductor element and an end portion (33b, 53b, 73b) thereof soldered to the top surface of the ceramic substrate, so that a top surface of the metal cap and a bottom surface of the semiconductor element fitting into the through-hole form a flat plane: and a heatsink member comprising a plate portion (35a, 55a, 75) which is soldered to the flat plane of the metal cap (33, 53, 73) and the semiconductor element (31, 51, 71) to complete a hermetic sealing of the semiconductor element.

公开(公告)号：DE3786861D1

公开(公告)日：1993-09-09

申请号：DE3786861

申请日：1987-01-22

Applicant: FUJITSU LTD

Inventor： SUGIMOTO MASAHIRO ,  WAKASUGI YASUMASA ,  HARADA SHIGEKI

IPC: H01L23/04 ,  H01L23/02 ,  H01L23/055 ,  H01L23/34 ,  H01L23/367

Abstract: A semiconductor device comprises a substrate (12), a semiconductor element (11) mounted on the substrate (12), a cap (13, 51, 62) having an opening (13c, 51a, 62a) smaller than the external size of the semiconductor element (11) for covering the semiconductor element (11) to provide a hermetic seal, and heatsink member (14, 63) mounted on the cap (13c, 51, 62) to cover the opening (13, 51a, 62a) and to make contact with the semiconductor element (11) via the opening (13c, 51a, 62a), so that heat generated by the semiconductor element (11) is conducted directly to the heatsink member (14, 63). A method of producing the semiconductor device comprises the steps of mounting the semiconductor element (11) on the substrate (12), covering the semiconductor element (11) by the cap (13, 51, 62) which is fixed to the substrate (12), and mounting the heatsink member (14, 63) on the cap (13, 51, 62) to cover the opening (13c, 51a, 62a) and to make contact with the semiconductor element (11) via the opening (13c, 51a, 62a).

公开(公告)号：HK46992A

公开(公告)日：1992-07-03

申请号：HK46992

申请日：1992-06-25

Applicant: FUJITSU LTD

Inventor： MIYAUCHI AKIRA ,  NISHIMOTO HIROSHI ,  OKIYAMA TADASHI ,  KITASAGAMI HIROO ,  SUGIMOTO MASAHIRO ,  TAMADA HARUO

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/04 ,  H01L23/057 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L23/64 ,  H01P1/00 ,  H01P3/08 ,  H01P5/00 ,  H01P5/02 ,  H01P5/08 ,  H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K3/40

Abstract: An integrated circuit (IC) device including a stacked layer unit (11) having a plurality of stacked ayers (11-1 to 11-6) each having an insulation layer (11-1b to 11-6b) and at least one conductive layer strip (11-1 a to 11-6a) formed on a surface of the nsulation layer, and at least one ship (3) mounted on the top of the insulation layer and having a plurality of circuit elements. The IC device also includes at least one first conductive member (13) formed in the stacked layer unit, having a low inductance for first signals applied thereto and operatively connecting the first signals to be transferred between the circuit elements; at least one second conductive member (14) formed in the stacked layer unit, having a higher inductance for the first signals than that of the first conductive member and operatively connecting second signals to be transferred between the circuit elements ; and, a package (21 to 24) enclosing the stacked layer unit, the chip, and the first and second conductive members, with a hermetic seal.

公开(公告)号：DE3678023D1

公开(公告)日：1991-04-18

申请号：DE3678023

申请日：1986-04-11

Applicant: FUJITSU LTD

Inventor： MIYAUCHI AKIRA ,  NISHIMOTO HIROSHI C O SUZUKI ,  OKIYAMA TADASHI ,  KITASAGAMI HIROO ,  SUGIMOTO MASAHIRO ,  TAMADA HARUO ,  EMORI SHINJI

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/04 ,  H01L23/057 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L23/64 ,  H01P1/00 ,  H01P3/08 ,  H01P5/00 ,  H01P5/02 ,  H01P5/08 ,  H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K3/40

Abstract: An integrated circuit (IC) device including a stacked layer unit (11) having a plurality of stacked ayers (11-1 to 11-6) each having an insulation layer (11-1b to 11-6b) and at least one conductive layer strip (11-1 a to 11-6a) formed on a surface of the nsulation layer, and at least one ship (3) mounted on the top of the insulation layer and having a plurality of circuit elements. The IC device also includes at least one first conductive member (13) formed in the stacked layer unit, having a low inductance for first signals applied thereto and operatively connecting the first signals to be transferred between the circuit elements; at least one second conductive member (14) formed in the stacked layer unit, having a higher inductance for the first signals than that of the first conductive member and operatively connecting second signals to be transferred between the circuit elements ; and, a package (21 to 24) enclosing the stacked layer unit, the chip, and the first and second conductive members, with a hermetic seal.