公开(公告)号：EP0814497A2

公开(公告)日：1997-12-29

申请号：EP97304224

申请日：1997-06-17

Applicant: SIEMENS AG ,  TOSHIBA KK ,  IBM

Inventor： ALSMEIER JOHANN ,  COTE DONNA R ,  LOH STEPHEN K ,  PARRIES PAUL C ,  GIFFORD GEORGE G ,  PREIN FRANK ,  LEVY MAX G ,  SUGIURA SOICHI

IPC: C23C16/30 ,  C23C16/56 ,  H01L21/205 ,  H01L21/28 ,  H01L21/30 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L23/31 ,  H01L29/78 ,  H01L21/22

CPC classification number: H01L29/66575 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3185 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises a hydrogen-rich (H-R) silicon nitride layer formed as part of the device structure. The H-R layer, which is formed by plasma-enhanced chemical vapor deposition, comprises hydrogen in an amount greater than that of conventional PLCVD nitride layers.

Abstract translation: 公开了一种用于制造包括形成用于促进表面状态钝化的结构的步骤的装置的方法。 该结构包括作为器件结构的一部分形成的富氢（H-R）氮化硅层。 通过等离子体增强化学气相沉积形成的H-R层包含比常规PLCVD氮化物层大的量的氢。

公开(公告)号：JPH1074912A

公开(公告)日：1998-03-17

申请号：JP21707897

申请日：1997-07-28

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To selectively reduce a leakage of an FET channel by making a gate oxide along the side of a second FET located extremely near to an ONO layer and thicker than a gate oxide between both FET sides. SOLUTION: In order to separately define an FET region 124, a trench 120 is etched inside a wafer 122 passing through a pad stack. An ONO layer 126 is formed in the common shape on the pad stack and inside the trench 120. A polysilicon layer is removed from the upper part of the pad stack, so that only polysilicon 132 may remain inside the trench 120. An oxide collar 134 is selectively formed inside the trench 120 along the ONO layer 126 on the polysilicon 132. The polysilicon layer is removed from the pad stack, so that polysilicon 140 remains only inside the trench 120. Then, the part along the side 142 of a channel, that is the part extremely close to the ONO layer 126, results in having a thicker gate oxide.

公开(公告)号：WO2011066035A3

公开(公告)日：2011-07-28

申请号：PCT/US2010050805

申请日：2010-09-30

Applicant: IBM ,  BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

IPC: H01L27/12

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L27/1203

Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

Abstract translation: 公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）位于绝缘体层上的半导体结构（100）。 衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。 此外，紧邻绝缘体层的半导体衬底的一部分（102）可以用稍高剂量的相同掺杂剂（111），具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。 可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加以及电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了任何得到的寄生电容器的阈值电压（Vt），从而降低了谐波行为。 在此还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：JPH11317404A

公开(公告)日：1999-11-16

申请号：JP6179999

申请日：1999-03-09

Applicant: SIEMENS AG ,  IBM

Inventor： COTE DONNA RIZZONE ,  COTE WILLIAM JOSEPH ,  NGUYEN SON VAN ,  KIRCHHOFF MARKUS ,  LEVY MAX G ,  HAUF MANFRED

IPC: H01L21/318 ,  H01L21/28 ,  H01L21/30 ,  H01L21/314 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To effectively passivate surface states by forming a device structure provided with an oxynitride layer formed through the plasma enhanced chemical vapor deposition method, and making the passivation of the surface state of the device easy. SOLUTION: An H-R silicon nitride layer is formed in a device structure 200 as the barrier or liner layer 260 of the wiring of devices. The structure 200 is provided with a gate 210, a drain, a source 230, and an STI region 240. The gate 210 contains a poly-layer 212, a silicide layer 214 of WSix , etc., and a silicon nitride cap layer 218, and the device structure 200 contains a spacer layer 250. The H-R layer is formed by the plasma-enhanced chemical vapor deposition(PECVD) method. In addition, an oxynitride is used in stead of the HR silicon nitride, so as to make the nitride function as a psssivation structure like a barrier layer. The oxynitride is formed, for example, by the PECVD method.

公开(公告)号：JPH10294362A

公开(公告)日：1998-11-04

申请号：JP9896898

申请日：1998-04-10

Applicant: IBM ,  SIEMENS AG

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To enable a process through which a shallow trench is filled in to be enhanced in manufacturing properties and yield by a method wherein an intermediate plane layer is formed, and the lower layer of a thick oxide is selectively etched to deteriorate in planarity. SOLUTION: An upper planar surface is formed so as to be flush with the fill-in upper surface 115 of a fill-in layer 110. A polish stop layer 130 is removed by the use of etching chemicals which are capable of etching both the polish stop layer 130 and a temporary fill-in layer 120, and an intermediate plane surface is kept unremoved leaving the cover part of the temporary fill-in layer 120 unremoved. A part of the fill-in layer 110 located outside the cover part of the temporary fill-in layer 120 is etched as deep as a point shallower than a trench by the use of chemicals which etch the fill-in layer 110 preferentially so as to enable the fill-in upper surface 115 of the fill-in layer 110 located above a reference surface to be flush with the fill-in upper surface 115 of the fill-in layer 110 located in the trench, whereby a planar surface is deteriorated in flatness.

公开(公告)号：JPH1174241A

公开(公告)日：1999-03-16

申请号：JP18232498

申请日：1998-06-29

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  WOLFGANG BERGNER ,  FIEGL BERNHARD ,  GEORGE R GOSSE ,  PARRIES PAUL ,  MATTHEW J SENDERBACH ,  TEIN-HAO WAN ,  WILLIAM C WILL ,  JUERGEN WITTMANN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To prevent damages to a substrate under a pad nitride layer, induced by CMP, by disposing the pad nitride layer under a conformally vapor-deposited dielectric layer and partly etching a first region on the dielectric layer disposed under a conformally vapor-deposited polysilicon layer, for removing the polysilicon layer. SOLUTION: A pad nitride layer 118 is evaporated onto a silicon mesa 114, and a TEOS layer (dielectric layer) 126 is evaporated conformally onto the pad nitride layer 118 and a silicon substrate 112. In addition, a polysilicon layer 130 is conformally evaporated onto the TEOS 126. Then, chemical and mechanical polishing(CMP) is used to planarize the polysilicon layer 130 downward to the surface of the TEOS layer 126, and a first region on the TEOS layer 126 disposed on the pad nitride 118 is thereby exposed. Further, the first region on the TEOS layer 126 is partly etched, using a first etching parameter, and thereafter the polysilicon layer 130 is removed.

公开(公告)号：JPH10107227A

公开(公告)日：1998-04-24

申请号：JP21707797

申请日：1997-07-28

Applicant: IBM ,  SIEMENS AG

Inventor： HAUE MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce a leakage of an FET channel by diffusing potassium along an ONO layer backing a trench on the surface of a wafer and forming a gate oxide on the exposed wafer surface. SOLUTION: A trench 120 is etched in a wafer 122 through a pad stack 121, a channel, a source, and a drain are formed in an FET region 124 defined above, and an ONO layer 126 backs the trench 120, passes through the surface 128 of the wafer 122 and extends on both sides of each trench 120 along the pad stack 121. An N polysilicon layer 130 is deposited on the ONO layer 126 and is removed so that polysilicon 132 is remained only in the trench 120, and the polysilicon layer 126 is polished to remove the residual ONO layer 124 from the pad stack 121. Consequently, by etching so that the polysilicon 132 remained in the trench is recessed from the surface 128, the FET in which a leakage of a channel is minimized can be formed.

公开(公告)号：JPH1074829A

公开(公告)日：1998-03-17

申请号：JP21707997

申请日：1997-07-28

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a field effect transistor(FET) which is separated on both sides by a trench. SOLUTION: This FET has a dielectric layer inside a separate trench 120 at least along one side face. This dielectric layer can be made into an ONO layer 120 and inside that layer, catalysts are diffused. Potassium is available as the catalyst. A gate oxide along the side face of the FET extremely close to the ONO layer 126 is thicker than a gate oxide between both the side faces.

公开(公告)号：SG50863A1

公开(公告)日：1998-07-20

申请号：SG1997002379

申请日：1997-07-07

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L27/105

Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

公开(公告)号：DE69737172T2

公开(公告)日：2008-01-03

申请号：DE69737172

申请日：1997-07-15

Applicant: SIEMENS AG ,  IBM

Inventor： HAUE MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/8242 ,  H01L29/78 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423

Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.