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    Method of manufacturing integrated circuit structure having pin diode
    1.
    发明专利
    Method of manufacturing integrated circuit structure having pin diode 有权
    制造具有二极管的集成电路结构的方法

    公开(公告)号：JP2011018920A

    公开(公告)日：2011-01-27

    申请号：JP2010193888

    申请日：2010-08-31

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： LANGGUTH GERNOT ,  MUELLER KARLHEINZ ,  WILLE HOLGER

    IPC: H01L31/10 ,  H01L27/06 ,  H01L27/146 ,  H01L31/105

    CPC classification number: H01L27/0664 ,  H01L27/14681

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit structure having a pin diode which has a simple design and high sensitivity and is suitable for use at radio frequencies.SOLUTION: A method of manufacturing the integrated circuit structure includes a process of forming a shape, including at least one step which is adjoined by a material 82 to be protected; a process of forming a protective layer which covers the step, a process of forming a spacer element layer after the protective layer is formed; a process of anisotropically etching the spacer element layer; a process of forming at least one spacer element at the step; a process of thinning or completely removing the protective layer in regions which are not covered by the spacer element with at least one remaining region 150 of the protective layer being left along the material 82 to be protected; a process of forming an effective layer, after the protective layer is thinned or removed; a process of patterning the effective layer, while removing the spacer element so as to protect the material 82 to be protected with the remaining region 150.

    Abstract translation: 要解决的问题：提供一种具有pin二极管的集成电路结构，其具有简单的设计和高灵敏度并且适用于射频。解决方案：一种制造集成电路结构的方法包括形成形状的过程， 包括由待保护的材料82邻接的至少一个台阶; 形成覆盖该台阶的保护层的工序，在形成保护层之后形成间隔元件层的工序; 对间隔元件层进行各向异性蚀刻的工序; 在该步骤形成至少一个间隔元件的工艺; 在保护层的至少一个剩余区域150沿待保护的材料82留下的情况下，在未被间隔元件覆盖的区域中使保护层变薄或完全去除的过程; 在保护层变薄或去除之后形成有效层的过程; 图案化有效层的过程，同时移除间隔元件，以保护被剩余区域150保护的材料82。

    METHOD FOR PRODUCING BIPOLAR TRANSISTORS IN A BICMOS PROCESS
    2.
    发明申请
    METHOD FOR PRODUCING BIPOLAR TRANSISTORS IN A BICMOS PROCESS 审中-公开
    用于生产双极晶体管，BiCMOS工艺

    公开(公告)号：WO0163644A3

    公开(公告)日：2002-03-14

    申请号：PCT/EP0101054

    申请日：2001-02-01

    Applicant: INFINEON TECHNOLOGIES AG ,  MUELLER KARLHEINZ

    Inventor： MUELLER KARLHEINZ

    IPC: H01L21/331 ,  H01L21/8249

    CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/66272

    Abstract: According to a method for producing bipolar single-polysilicon transistors which can be integrated into a BICMOS, an emitter contact hole (13) is etched out through a base contact layer (10) as far as a collector area (2, 7). The base layer (8) and the emitter (15) are then formed in the emitter contact hole (13).

    Abstract translation: 在一可组合在单个双极晶体管的多晶硅到集电极区域的BiCMOS一个制造方法（2，7）由一基极接触层（10）蚀刻出发射极接触孔（13）。 随后，形成在发射极接触孔（13）基极层（8）和所述发射器（15）。

    METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT WITH A BIPOLAR TRANSISTOR AND A HETERO BIPOLAR TRANSISTOR
    3.
    发明申请
    METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT WITH A BIPOLAR TRANSISTOR AND A HETERO BIPOLAR TRANSISTOR 审中-公开
    METHOD FOR制造集成电路与集成电路具有双极晶体管和杂

    公开(公告)号：WO03096412A2

    公开(公告)日：2003-11-20

    申请号：PCT/EP0305001

    申请日：2003-05-13

    Applicant: INFINEON TECHNOLOGIES AG ,  DAHL CLAUS ,  MUELLER KARLHEINZ ,  WAGNER CAJETAN

    Inventor： DAHL CLAUS ,  MUELLER KARLHEINZ ,  WAGNER CAJETAN

    IPC: H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

    CPC classification number: H01L27/0623 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825

    Abstract: In order to integrate an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is produced (322) in a base area of the hetero bipolar transistor after structuring (320) a collector structure for both types of transistors, wherein the placeholder layer is not present in a base area of the bipolar transistor. The base of the bipolar transistor is covered (326) once the base of the bipolar transistor has been produced (324), whereupon the placeholder layer is removed and the base (328) of the hetero bipolar transistor is then produced on the site from which the placeholder layer has been removed. The emitter structure is then equally produced (330) for both types of transistors so that an integrated circuit comprising the bipolar transistors and the hetero bipolar transistors is obtained, the collector structures and/or the emitter structures of which consist of identical production layers. This makes it possible to produce space-saving and economical integrated circuits profiting from the advantages of both transistor types.

    Abstract translation: 用于根据图案化（320）的集电极结构两种晶体管类型的具有异质结双极晶体管的npn双极晶体管的集成是在异质（322），其中所述占位符层不存在于所述双极晶体管的基区的基极区中产生的占位符层。 双极晶体管的基极的生成（324）后，将双极晶体管的基极被覆盖（326），于是在牺牲层被去除，异质结双极型晶体管的基极（328）产生，其中该占位符层已被移除。 其中的发射极结构被同时产生这两种类型的晶体管（330），使得存在一种集成电路，其包括双极晶体管和异质其集电极结构和/或发射器的结构相同的底涂层组成。 因此节省空间和成本效益的集成电路可以由从两种类型的晶体管的优点在于益处。

    METHOD FOR THE EPITAXIAL DEPOSITION OF LAYERS
    5.
    发明申请
    METHOD FOR THE EPITAXIAL DEPOSITION OF LAYERS 审中-公开
    方法外延沉积分层损伤

    公开(公告)号：WO2004064131A3

    公开(公告)日：2004-10-07

    申请号：PCT/DE0304244

    申请日：2003-12-23

    Applicant: INFINEON TECHNOLOGIES AG ,  LANGGUTH GERNOT ,  MUELLER KARLHEINZ ,  WILBERTZ CHRISTOPH ,  WILLE HOLGER

    Inventor： LANGGUTH GERNOT ,  MUELLER KARLHEINZ ,  WILBERTZ CHRISTOPH ,  WILLE HOLGER

    IPC: H01L21/20 ,  H01L21/22

    CPC classification number: H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

    Abstract: Disclosed is a method for the epitaxial deposition of layers, according to which a low-doped epitaxial layer is applied to highly doped areas that are incorporated into a silicon substrate. The aim of the invention is to ensure functionality of the components that are to be produced while effectively preventing autodoping. Said aim is achieved by applying a high-resistance silicon layer to the highly doped areas before the epitaxial layer is applied, the other areas being covered or the high-resistance layer being locally removed from the other areas. The epitaxial layer is then deposited onto the high-resistance silicon layer located above the highly doped areas and onto the silicon layer located outside the highly doped areas. Autodoping of the epitaxial layer is effectively prevented by the high-resistance silicon layer.

    Abstract translation: 本发明涉及一种用于其中在高掺杂区域，其在硅衬底掺入的低掺杂外延层，被施加的目的是保证所制造的组件的可操作性，并有效地抑制汽车掺杂层的外延沉积的方法 ， 这是这样实现的高电阻硅层上的高掺杂区域上沉积外延层之前施加，与其他区域要么覆盖或在其它区域高电阻层局部除去。 随后，将外延层沉积在高掺杂区域的高电阻硅层和硅衬底的高掺杂区的外侧。 由高电阻硅层可以有效地抑制在外延层的自动掺杂。

    ESD-PROTECTION STRUCTURES FOR SEMICONDUCTOR COMPONENTS
    6.
    发明申请
    ESD-PROTECTION STRUCTURES FOR SEMICONDUCTOR COMPONENTS 审中-公开
    ESD保护结构半导体器件

    公开(公告)号：WO2005117133A2

    公开(公告)日：2005-12-08

    申请号：PCT/DE2005000896

    申请日：2005-05-17

    Applicant: INFINEON TECHNOLOGIES AG ,  RUNDE MICHAEL ,  LANGGUTH GERNOT ,  ROESCHLAU KLAUS ,  MUELLER KARLHEINZ

    Inventor： RUNDE MICHAEL ,  LANGGUTH GERNOT ,  ROESCHLAU KLAUS ,  MUELLER KARLHEINZ

    IPC: H01L27/02 ,  H01L29/861

    CPC classification number: H01L27/0255 ,  H01L29/861

    Abstract: The invention relates to an ESD-protection structure for semiconductor elements, consisting of at least one semiconductor diode, whose p- and n-conductive zones are in electric contact with respective regions of the same charge carrier type of the element to be protected of the semiconductor component at a first and second contact point. The aim of the invention is to provide ESD-protection structures that are cost-effective to produce and that permit higher current carrying capacities with at least a comparable space requirement or at least comparable current carrying capacities with a reduced space requirement. To achieve this: a first zone of one charge carrier type of the semiconductor diode covers at least some sections of the inner surface of a channel that is configured in the semiconductor substrate of the semiconductor element and a second zone of the other charge carrier type adjoins the first zone in the vicinity of said channel; the first zone is configured from a polysilicon that has an appropriate conductive doping; and the channel area that is not filled by the polysilicon is filled with a dielectric.

    Abstract translation: 本发明涉及一种ESD保护结构用于半导体器件，其包括至少一个半导体二极管，所述p型和n型导电与部件的相同的载流子类型的每个区域在第一和第二接触点要被保护的半导体设备的电接触区域。 它是基于与较高电流承载容量，可以实现显示器产生成本ESD保护结构的物体上时至少相当的空间需求或至少相当的电流承载能力具有较小足迹。 根据本发明，该目的是这样的第一区，所述半导体二极管的一个载流子类型，一个形成于半导体器件沟道中，其它载流子类型的第二区的所述半导体衬底的内表面相邻，所述第一区形成至少部分地覆盖所述第一区域和在所述的信道环境来实现在 通过相应导电掺杂的多晶硅形成，且没有被多晶硅自由沟道区域填充填充有电介质。

    METHOD FOR PRODUCING A DMOS TRANSISTOR
    8.
    发明申请
    METHOD FOR PRODUCING A DMOS TRANSISTOR 审中-公开
    制造DMOS晶体管的方法

    公开(公告)号：WO0235600A2

    公开(公告)日：2002-05-02

    申请号：PCT/EP0112035

    申请日：2001-10-17

    Applicant: INFINEON TECHNOLOGIES AG ,  MUELLER KARLHEINZ ,  WAGNER CAJETAN ,  ROESCHLAU KLAUS

    Inventor： MUELLER KARLHEINZ ,  WAGNER CAJETAN ,  ROESCHLAU KLAUS

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8234

    CPC classification number: H01L29/66681 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66689

    Abstract: The invention relates to a method for producing a DMOS transistor structure. The invention is advantageous in that a protective layer (14) is used to protect the already essentially completed DMOS transistor structure from the negative effects of additional process steps. According to the invention, the DMOS gate electrode is not customarily structured, as in the prior art, by using a single lithography step, rather the structuring of the DMOS gate electrode is split between two lithography steps. In a first lithography step, essentially only the source region (9) of the DMOS transistor structure is opened, whereby the electrode layer still present can be used as a mask for the subsequent production of the body region (8).

    Abstract translation: 根据本发明，提供了一种用于制造DMOS晶体管结构的方法。 本发明具有以下优点：使用保护层（14）保护已经基本完成的DMOS晶体管结构免受进一步处理步骤的负面影响。 根据本发明，DMOS栅电极不像现有技术中习惯的那样用单个光刻步骤来图案化，而是将DMOS栅电极的结构分成两个光刻步骤。 在第一光刻步骤中，基本上仅打开DMOS晶体管结构的源极区域（9）。 因此剩余的电极层可以用作随后生产体区（8）的掩模。

    METHOD FOR THE PRODUCTION OF AN ANTI-REFLECTING SURFACE ON OPTICAL INTEGRATED CIRCUITS
    10.
    发明申请
    METHOD FOR THE PRODUCTION OF AN ANTI-REFLECTING SURFACE ON OPTICAL INTEGRATED CIRCUITS 审中-公开
    用于在光集成电路上产生抗反射表面的方法

    公开(公告)号：WO2005045941A2

    公开(公告)日：2005-05-19

    申请号：PCT/DE2004002340

    申请日：2004-10-20

    Applicant: INFINEON TECHNOLOGIES AG ,  LANGGUTH GERNOT ,  MUELLER KARLHEINZ ,  WILLE HOLGER

    Inventor： LANGGUTH GERNOT ,  MUELLER KARLHEINZ ,  WILLE HOLGER

    IPC: H01L31/0216 ,  H01L31/0232 ,  H01L31/0236 ,  H01L31/18

    CPC classification number: H01L31/1804 ,  H01L31/02363 ,  Y02E10/547 ,  Y02P70/521

    Abstract: The invention relates to a method for the production of an anti-reflecting surface on optical integrated circuits in order to improve light absorption in photodetectors. The aim of the invention is to create a method which can be produced with minimum input and in an economical manner, for the production of an anti-reflecting surface on optical integrated circuits, said method being compatible with IC technology systems and single device technology systems. Said aim is achieved by virtue of the fact that a controlled hard mask grid is produced in a photolithographic manner on the surface of the photodetector; a structure corroding step is then carried out until a predetermined depth in the silicon is reached, such that inverse pyramids which are arranged in an evenly distributed manner are produced and that an interrupted anode or a cathode of the photodetector is reproduced by another implantation step during corrosion.

    Abstract translation: 本发明涉及在光学集成电路上制造抗反射表面的方法，用于改善光电探测器中光的吸收。 本发明的目的是提供一种用于在光集成电路上制造抗反射表面的低成本方法，其与IC和单个器件技术兼容。 这是这样实现的一个常规硬掩模光栅形成在光电检测器光刻的表面上，在随后一个Strukturätzschritt执行到在硅的预定深度，从而形成规则排列的分布逆金字塔以及在蚀刻期间 通过进一步的植入步骤恢复光电探测器的破碎的阳极或阴极。

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