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    MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY
    1.
    发明专利
    MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY 审中-公开

    公开(公告)号：JP2004005924A

    公开(公告)日：2004-01-08

    申请号：JP2003080601

    申请日：2003-03-24

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA CORP

    Inventor： TAKASHIMA DAISABURO ,  SHIRATAKE SHINICHIRO ,  JOACHIM HANS OLIVER ,  ROEHR THOMAS

    IPC: G11C8/08 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: PROBLEM TO BE SOLVED: To provide a chain structure memory IC with improved reliability by driving a wordline by a mechanism of multi-step voltage, boosting a voltage only when a gate is required and reducing a load to a gate oxidation film. SOLUTION: This invention related to the chain memory IC which drives the wordline by using a mechanism of two-step voltage. During a suspended state, the wordline is maintained by a first logic 1 voltage level. For memory call, a selected wordline is driven by earthing, and on the other hand, a wordline which is not selected is driven by a boosted voltage. The first logic 1 voltage level is lower than the boosted voltage. This reduces the load to the gate oxidation film of a transistor. COPYRIGHT: (C)2004,JPO

    SIGNAL MARGIN TEST CIRCUIT OF A MEMORY
    2.
    发明申请
    SIGNAL MARGIN TEST CIRCUIT OF A MEMORY 审中-公开
    信号记忆测试电路

    公开(公告)号：WO2004025664A3

    公开(公告)日：2004-07-08

    申请号：PCT/EP0309775

    申请日：2003-09-03

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

    Inventor： TAKASHIMA DAISABURO ,  JACOB MICHAEL ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

    IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

    CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C2029/1204 ,  G11C2029/5004

    Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bitlines. During a read access, a selected memory cell produces a differential read signal on the bitlines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.

    Abstract translation: 公开了一种用于在存储器访问期间测试差分读取信号的测试电路。 测试电路耦合到一对位线。 在读取访问期间，所选择的存储器单元在位线上产生差分读取信号。 当测试电路被激活时，差分读取信号的幅度是变化的。 这使得能够容易地测试例如存储器IC中的读取信号余量。

    FERROELECTRIC MEMORY DEVICE
    3.
    发明申请
    FERROELECTRIC MEMORY DEVICE 审中-公开
    电磁存储器件

    公开(公告)号：WO2004109705A2

    公开(公告)日：2004-12-16

    申请号：PCT/JP2004008288

    申请日：2004-06-08

    Applicant: TOSHIBA KK ,  INFINEON TECHNOLOGIES AG ,  HOYA KATSUHIKO ,  TAKASHIMA DAISABURO ,  REHM NOBERT

    Inventor： HOYA KATSUHIKO ,  TAKASHIMA DAISABURO ,  REHM NOBERT

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105

    CPC classification number: G11C11/22

    Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array, and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array, the first dummy bit line having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and including a cell transistor and a ferroelectric capacitor.

    Abstract translation: 铁电存储器件包括具有以矩阵形式布置的存储单元的存储单元阵列。 每个存储单元包括单元晶体管和铁电电容器。 它还包括布置在存储单元阵列的端部上的位线之外的第一虚位位线，并且以与间距相同的间隔与布置在存储单元阵列的端部上的位线分离 在存储单元阵列中的位线之间，具有与位线相同宽度的第一虚位线以及连接到第一虚位线并包括单元晶体管和铁电电容器的第一虚存储单元。

    REDUCING EFFECTS OF NOISE COUPLING IN INTEGRATED CIRCUITS WITH MEMORY ARRAYS
    4.
    发明申请
    REDUCING EFFECTS OF NOISE COUPLING IN INTEGRATED CIRCUITS WITH MEMORY ARRAYS 审中-公开
    噪声耦合在集成电路与存储器阵列中的降低效应

    公开(公告)号：WO2004051666A3

    公开(公告)日：2005-02-24

    申请号：PCT/EP0312715

    申请日：2003-11-13

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK ,  JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  TAKASHIMA DAISABURO

    Inventor： JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  TAKASHIMA DAISABURO

    IPC: G11C11/22

    CPC classification number: G11C11/22

    Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

    Abstract translation: 公开了一种减少存储器阵列中的噪声耦合的方法。 存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。 存储器单元被布置成具有耦合到读出放大器的第一和第二位线的列。 在存储器访问期间，至少相邻的位线对不被激活。 选定的位线对或对配有一条平行线脉冲。

    6.
    发明专利
    未知

    公开(公告)号：DE10393791T5

    公开(公告)日：2005-10-06

    申请号：DE10393791

    申请日：2003-11-13

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

    Inventor： ROEHR THOMAS ,  JACOB MICHAEL ,  REHM NORBERT ,  TAKASHIMA DAISABURO

    IPC: G11C11/22

    Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

    9.
    发明专利
    未知

    公开(公告)号：DE60327215D1

    公开(公告)日：2009-05-28

    申请号：DE60327215

    申请日：2003-08-11

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

    Inventor： JOACHIM HANS-OLIVER ,  TAKASHIMA DAISABURO

    IPC: G11C11/22 ,  G11C5/14 ,  G11C29/00

    Abstract: An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference cells are provided. A bitline includes a reference cell. The bitlines of the memory block are divided into groups or bitlines. The reference cells within a group are interconnected to average out the reference cell charge variation to improve the sensing window.

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