公开(公告)号：JP2014059920A

公开(公告)日：2014-04-03

申请号：JP2014000371

申请日：2014-01-06

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  DION ROGERS ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus, system that enables effective communication between instruction set architecture-based sequencers having heterogeneous resources.SOLUTION: The method comprises: directly communicating a request from a user-level application to an accelerator coupled to a first instruction sequencer via the first instruction sequencer, where the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer; providing the request to the accelerator via an exo-skeleton associated with the accelerator; and performing a first function in the accelerator in response to the request in parallel with a second function in the first instruction sequencer.

Abstract translation: 要解决的问题：提供一种使得能够在具有异构资源的指令集体系结构的定序器之间有效通信的方法，装置，系统。解决方案：该方法包括：将来自用户级应用的请求直接传达到耦合到 所述第一指令定序器经由所述第一指令定序器，其中所述加速器包括相对于所述第一指令定序器的异质资源; 通过与加速器相关联的外部骨架向加速器提供请求; 以及响应于与第一指令定序器中的第二功能并行的请求在加速器中执行第一功能。

公开(公告)号：JP2011076639A

公开(公告)日：2011-04-14

申请号：JP2011007496

申请日：2011-01-18

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： BIGBEE BRYANT ,  HANKINS RICHARD A ,  WANG HONG ,  DIEP TRUNG ,  XINMIN TIAN ,  KAUSHIK CHIV ,  SHEN JOHN ,  MALLICK ASIT ,  GIRKAR MILLIND ,  SETHI PRASHANT ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  HELD JAMES PAUL

IPC: G06F9/46

CPC classification number: G06F9/4843

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and system for scheduling OS-independent 'shreds' without intervention of an operating system.
SOLUTION: For at least in one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在不介入操作系统的情况下调度与OS无关的“碎片”的方法，装置和系统。 解决方案：至少在一个实施例中，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的定序器上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007242003A

公开(公告)日：2007-09-20

申请号：JP2007028172

申请日：2007-02-07

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： JACOBSON QUINN ,  BRACY ANNE ,  WANG HONG ,  SHEN JOHN ,  HAMMARLUND PER ,  MERTEN MATTHEW ,  SRINIVAS SURESH ,  DOSHI KSHITIJ ,  CHINYA GAUTHAM ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA ,  SHEAFFER GAD

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F11/3471 ,  G06F11/3648 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/145 ,  G06F2201/865

Abstract: PROBLEM TO BE SOLVED: To provide a method for efficiently check memory properties in a microprocessor system. SOLUTION: Attribute bits indicating that a program has recently checked that a block of memory is appropriate for the current portion of the program to access, indicating that the program has analyzed this block of memory by a performance monitoring tool, or having properties such as access right are included in a cache memory line, and correspond to only one software thread of the program having multisoftware threads. The attribute bits are used to check the memory state of an address used by the program. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于有效地检查微处理器系统中的存储器特性的方法。 解决方案：指示程序最近检查一个存储器块是否适合于程序当前部分访问的属性位，指示程序已经由性能监视工具分析了该块存储器，或者具有属性 例如访问权被包括在高速缓存存储器行中，并且仅对应于具有多软件线程的程序的一个软件线程。 属性位用于检查程序使用的地址的内存状态。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2013191244A

公开(公告)日：2013-09-26

申请号：JP2013140714

申请日：2013-07-04

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： BIGBEE BRYANT ,  HANKINS RICHARD A ,  WANG HONG ,  DIEP TRUNG ,  XINMIN TIAN ,  KAUSHIK CHIV ,  JOHN SHEN ,  MALLICK ASIT ,  GIRKAR MILLIND ,  SETHI PRASHANT ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  HELD JAMES PAUL

IPC: G06F9/46

CPC classification number: G06F9/4843

Abstract: PROBLEM TO BE SOLVED: To provide various embodiments of a method, a device and a system for scheduling OS independent 'shred' without interposition of an operating system.SOLUTION: For at least one embodiment, a shred is scheduled for execution not by an operating system but by a scheduler routine. The scheduler routine can travel on the respective validated sequencers. A scheduler can acquire a shred descriptor from a queue system. Next, a sequencer associated with the scheduler can execute the shred to be described by the descriptor. Other embodiments are also described, and claimed.

Abstract translation: 要解决的问题：提供方法，设备和系统的各种实施例，用于在不插入操作系统的情况下调度独立于OS的“独立”操作系统。解决方案：对于至少一个实施例，碎片被安排执行而不是通过操作 系统，但通过调度程序。 调度程序可以在相应的经过验证的定序器上运行。 调度程序可以从队列系统中获取碎片描述符。 接下来，与调度器相关联的定序器可以执行由描述符描述的细丝。 还描述和要求保护其他实施例。

公开(公告)号：JP2011103132A

公开(公告)日：2011-05-26

申请号：JP2011001163

申请日：2011-01-06

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： CHINYA GAUTHAM ,  WANG HONG ,  ZOU XIANG ,  KAUSHIK CHIV ,  BIGBEE BRYANT ,  SHEN JOHN ,  DIEP TRUNG ,  AGGARWAL ANIL ,  PATEL BAIJU V ,  HELD JAMES PAUL ,  SETHI PRASHANT ,  HANKINS RICHARD A ,  REID JOHN L

IPC: G06F9/46

CPC classification number: G06F9/45533 ,  G06F9/4881

Abstract: PROBLEM TO BE SOLVED: To provide a method for scheduling threads without restricting the scheduling to the small number of threads and without exerting a negative influence on performance for a system that supports concurrent execution of a plurality of software threads such as SMT, SMP and/or CMP systems. SOLUTION: Shreds 130 to 136 are generated and managed by a user-level program and scheduled so as to run on a sequencer sequestered from an operating system 140. An abstraction layer provides respective functions of sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于调度线程的方法，而不限制对少量线程的调度，并且对支持多个软件线程（例如SMT）的并发执行的系统的性能不产生负面影响， SMP和/或CMP系统。 解决方案：碎片130至136由用户级程序生成和管理，并被调度以便在从操作系统140隔离的定序器上运行。抽象层提供封存逻辑，代理执行逻辑，转换的相应功能 检测和碎片悬挂逻辑，以及定序器算术逻辑。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007102781A

公开(公告)日：2007-04-19

申请号：JP2006266590

申请日：2006-09-29

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： CHINYA GAUTHAM ,  WANG HONG ,  SETHI PRASHANT ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEN JOHN ,  HANKINS RICHARD ,  ZOU XIANG ,  PATEL BAIJU ,  BRANDT JASON ,  AGGARWAL ANIL ,  REID JOHN

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/461

Abstract: PROBLEM TO BE SOLVED: To provide a method for generating a persistent user-level thread.
SOLUTION: Embodiments of the invention provide a method of creating, based on an operating-system (OS)-scheduled thread running on an OS-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an OS-sequestered sequencer independently of context switch activities on the OS-scheduled thread. The OS-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional OS-visible sequencer to provide OS services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于生成持久用户级线程的方法。 解决方案：本发明的实施例提供了一种基于在OS可见定序器上运行并使用指令集扩展的操作系统（OS）调度的线程来创建持久的用户级线程来运行的方法 独立于操作系统调度的线程上的上下文切换活动的OS隔离的定序器。 OS调度的线程和持久用户级线程可以共享公共的虚拟地址空间。 本发明的实施例还可以提供一种使服务线程在附加的OS可见定序器上运行以向持久用户级线程提供OS服务的方法。 本发明的实施例还可以提供其装置，系统和机器可读介质。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2011146077A

公开(公告)日：2011-07-28

申请号：JP2011101385

申请日：2011-04-28

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。 该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011023032A

公开(公告)日：2011-02-03

申请号：JP2010204922

申请日：2010-09-13

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： WANG HONG ,  SHEN JOHN ,  GROCHOWSKI ED ,  HELD JAMES PAUL ,  BIGBEE BRYANT ,  KAUSHIK SHIVNANDAN D ,  CHINYA GAUTHAM ,  ZOU XIANG ,  HAMMARLUND PER ,  TIAN XINMIN ,  AGGARWAL ANIL ,  RODGERS SCOTT DION ,  PATEL BAIJU V ,  RICHARD HANKINS

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/4843

Abstract: PROBLEM TO BE SOLVED: To provide a mechanism for scheduling user-level threads so that the user-level threads can be executed on a processor that is not directly managed by an OS.
SOLUTION: User-level threads on a first instruction sequencer are managed in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least (1) a field that makes reference to one or more instruction sequencers or (2) implicitly references with a pointer to a code that specifically addresses one or more instruction sequencers when the code is executed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于调度用户级线程的机制，使得可以在不由OS直接管理的处理器上执行用户级线程。 解决方案：响应于在应用级程序的控制下的第二指令定序器上执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有（1）引用一个或多个指令定序器的字段，或（2）隐含地引用指向代码执行时特定地址一个或多个指令定序器的代码的指针。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007183943A

公开(公告)日：2007-07-19

申请号：JP2006348294

申请日：2006-12-25

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

IPC: G06F9/38 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system allowing effective communication between respective instruction set architecture base sequencers having heterogeneous resources. SOLUTION: This method is constructed of steps for: directly transmitting a request to an accelerator, which is connected via a first instruction sequencer and has heterogeneous resources about the first instruction sequencer, from a user level application to the first instruction sequencer; offering the request to the accelerator via an exoskeleton about the accelerator; and executing a first function in the accelerator in response to the request in parallel to a second function in the first instruction sequencer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种允许具有异构资源的各个指令集架构基本定序器之间有效通信的方法，设备和系统。 解决方案：该方法由以下步骤构成：用于通过第一指令定序器将与第一指令定序器相关的异构资源从用户级应用程序直接传送到加速器的请求到第一指令定序器; 通过关于加速器的外骨骼向加速器提出要求; 以及响应于与第一指令定序器中的第二功能并行的请求，在加速器中执行第一功能。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2007002550A3

公开(公告)日：2007-05-31

申请号：PCT/US2006024727

申请日：2006-06-23

Applicant: INTEL CORP ,  JACOBSON QUINN ,  WANG HONG ,  SHEN JOHN ,  CHINYA GAUTHAM ,  HAMMERLUND PER ,  ZOU XIANG ,  BIGBEE BRYANT ,  KAUSHKI SHIVNANDAN

Inventor： JACOBSON QUINN ,  WANG HONG ,  SHEN JOHN ,  CHINYA GAUTHAM ,  HAMMERLUND PER ,  ZOU XIANG ,  BIGBEE BRYANT ,  KAUSHKI SHIVNANDAN

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

Abstract translation: 处理器可以包括地址监视器表和原子更新表以支持推测线程。 处理器还可以包括一个或多个寄存器以保持与推测线程的执行相关联的状态。 处理器可以支持以下原语中的一个或多个：写入状态的寄存器的指令，触发提交缓冲存储器更新的指令，读取状态的状态寄存器的指令，和/或 指令来清除与陷阱/异常/中断处理相关的状态位之一。 其他实施例也被描述和要求保护。