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    Instruction set extension using 3-byte escape opcode
    1.
    发明专利
    Instruction set extension using 3-byte escape opcode 有权
    使用3字节ESCAPE操作码的指令集扩展

    公开(公告)号：JP2005025741A

    公开(公告)日：2005-01-27

    申请号：JP2004188541

    申请日：2004-06-25

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： COKE JAMES ,  RUSCITO PETER ,  TAHIR MASOOD ,  JACKSON DAVID ,  NAYDENOV VES ,  RODGERS DION ,  TOLL BRET ,  BINNS FRANK

    IPC: G06F9/30 ,  G06F9/00 ,  G06F9/315 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

    CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

    Abstract: PROBLEM TO BE SOLVED: To provide an effective method for extending an instruction set without increasing complexity of hardware. SOLUTION: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such that the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant for determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供扩展指令集而不增加硬件复杂度的有效方法。 公开了一种用于解码可变长度指令集中的指令的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，使得可以使用相同的一组输入来确定用于新的转义操作码值之一的操作码映射中的每个指令的长度，其中每个输入与确定每个指令的长度有关 新的操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。 版权所有（C）2005，JPO＆NCIPI

    Apparatuses, methods, and systems for installing virtual events in layered virtual architecture
    2.
    发明专利
    Apparatuses, methods, and systems for installing virtual events in layered virtual architecture 审中-公开
    用于在层级虚拟架构中安装虚拟事件的装置，方法和系统

    公开(公告)号：JP2009015848A

    公开(公告)日：2009-01-22

    申请号：JP2008169354

    申请日：2008-06-27

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： BENNETT STEVEN M ,  ANDERSON ANDREW V ,  NEIGER GILBERT ,  RODGERS DION ,  HUNTLEY BARRY E ,  SMITH LAWRENCE O

    IPC: G06F9/46

    CPC classification number: G06F9/45558 ,  G06F2009/45566

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus, method and system for installing a virtual event in a layered virtual architecture.
    SOLUTION: In one embodiment, an apparatus includes virtual machine entry logic, recognition logic, and evaluation logic. The virtual machine entry logic starts to transfer control of the apparatus from a host to a guest running on a virtual machine. The recognition logic recognizes a request from the host to install a virtual event into the virtual machine. The evaluation logic specifies an intervening monitor to handle the virtual event.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在分层虚拟架构中安装虚拟事件的装置，方法和系统。 解决方案：在一个实施例中，设备包括虚拟机入口逻辑，识别逻辑和评估逻辑。 虚拟机入口逻辑开始将设备的控制从主机传送到在虚拟机上运行的guest虚拟机。 识别逻辑识别主机将虚拟事件安装到虚拟机中的请求。 评估逻辑指定一个中间监视器来处理虚拟事件。 版权所有（C）2009，JPO＆INPIT

    Virtualization of physical memory in virtual machine system
    3.
    发明专利
    Virtualization of physical memory in virtual machine system 审中-公开
    虚拟机系统中物理存储器的虚拟化

    公开(公告)号：JP2006196005A

    公开(公告)日：2006-07-27

    申请号：JP2006006606

    申请日：2006-01-13

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： BENNETT STEVEN ,  ANDERSON ANDREW ,  NEIGER GILBERT ,  SANKARAN RAJESH ,  UHLIG RICHARD ,  SMITH LARRY III ,  RODGERS DION

    IPC: G06F12/10 ,  G06F9/46

    CPC classification number: G06F12/109 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/1483 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/657

    Abstract: PROBLEM TO BE SOLVED: To provide a processor, a method, and a system for a virtual system. SOLUTION: In a remapping method for a guest physical memory via the virtualization of a host machine, respective virtual machines such as a virtual machine A 242 and a virtual machine B 257 individually give virtual processors 245 and 255 to guest software operated on the virtual machines. The respective machines give guest physical memories 240 and 250 serving as the abstraction of a physical memory to a guest operating system or the other guest software. When the guest software is operated on the virtual machines 242 and 257, operation is actually carried out by a host machine 267 on the host processor 265 using the host physical memory 260. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供用于虚拟系统的处理器，方法和系统。 解决方案：在通过主机的虚拟化的客户物理存储器的重映射方法中，诸如虚拟机A 242和虚拟机B 257之类的各自的虚拟机分别为虚拟处理器245和255提供给在 虚拟机。 相应的机器给宾客物理存储器240和250作为物理存储器对客户机操作系统或其他客户软件的抽象。 当客户软件在虚拟机242和257上运行时，实际上由主机256上的主机267使用主机物理存储器260执行操作。（C）版权所有（C）2006，JPO＆NCIPI

    Instruction set architecture-based inter-sequencer communication with heterogeneous resource
    8.
    发明专利
    Instruction set architecture-based inter-sequencer communication with heterogeneous resource 审中-公开
    具有异构资源的基于指令集架构的串行间通信

    公开(公告)号：JP2011146077A

    公开(公告)日：2011-07-28

    申请号：JP2011101385

    申请日：2011-04-28

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

    IPC: G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

    Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。 该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。 版权所有（C）2011，JPO＆INPIT

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