公开(公告)号：US10296217B2

公开(公告)日：2019-05-21

申请号：US15618170

申请日：2017-06-09

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Mark A. Schmisseur ,  Raymond S. Tetrick ,  Robert J. Royer, Jr. ,  David B. Minturn ,  Shane Matthews

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F13/28

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

公开(公告)号：US09971691B2

公开(公告)日：2018-05-15

申请号：US15263148

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Blaise Fanning

IPC: G06F12/0846 ,  G06F12/0831 ,  G11C7/10 ,  G06F12/0811

CPC classification number: G06F12/0851 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/2515 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/621 ,  G11C7/1072

Abstract: Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

公开(公告)号：US09736071B2

公开(公告)日：2017-08-15

申请号：US14580073

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F3/00 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F5/06 ,  H04L12/835

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US09703502B2

公开(公告)日：2017-07-11

申请号：US15214005

申请日：2016-07-19

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

公开(公告)号：US09602408B2

公开(公告)日：2017-03-21

申请号：US14144320

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F5/06

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US20160034345A1

公开(公告)日：2016-02-04

申请号：US14775848

申请日：2014-02-26

Applicant: Robert J. ROYER, JR. ,  Blaise FANNING ,  Eng Hun OOI ,  INTEL CORPORATION

Inventor： Robert J. Royer, Jr. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控​​制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。

公开(公告)号：US09213666B2

公开(公告)日：2015-12-15

申请号：US14497567

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Eran Tamari ,  Mikal C. Hunsaker ,  Sridhar Lakshmanamurthy ,  Michael T. Klinglesmith ,  Blaise Fanning

IPC: G06F13/14 ,  G06F13/42 ,  G06F13/366 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/4036

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

公开(公告)号：US09098402B2

公开(公告)日：2015-08-04

申请号：US13725502

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Blaise Fanning ,  Mark A. Schmisseur ,  Raymond S. Tetrick ,  Robert J. Royer, Jr. ,  David B. Minturn ,  Shane Matthews

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/28 ,  G06F2212/7206

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Abstract translation: 公开了用于配置固态驱动器（SSD）以在存储模式或存储器模式下操作的示例。 在一些示例中，可以在具有一个或多个非易失性存储器阵列的SSD的控制器处接收一个或多个配置命令。 SSD可以被配置为基于一个或多个配置命令以存储模式，存储模式或者存储模式或存储器模式的组合中的至少一个进行操作。 其他的例子被描述和要求保护。

公开(公告)号：US09075929B2

公开(公告)日：2015-07-07

申请号：US14578720

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/42 ,  G06F13/368

CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

公开(公告)号：US09071528B2

公开(公告)日：2015-06-30

申请号：US13730024

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.