公开(公告)号：US09543516B2

公开(公告)日：2017-01-10

申请号：US14317255

申请日：2014-06-27

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Jinhong Tong ,  Randall Higuchi ,  Imran Hashim ,  Vidyut Gopal

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1658

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract translation: 制造具有降低的成形电压的RRAM电阻式开关元件的方法包括掺杂以在电介质膜中产生氧缺陷。 电介质膜中的氧缺乏促进导电通路的形成。

公开(公告)号：US09178145B2

公开(公告)日：2015-11-03

申请号：US14264475

申请日：2014-04-29

Applicant: Intermolecular Inc.

Inventor： Nitin Kumar ,  Tony P. Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jinhong Tong

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract translation: 提供电阻式开关存储器元件，其可以包含由无电金属形成的化学金属电极和金属氧化物。 电阻式开关存储器元件可以表现出双稳态，并且可以用于高密度多层存储器集成电路中。 诸如镍基材料的无电导电材料可以选择性地沉积在硅晶片或其它合适的衬底上的导体上。 无电导电材料可以被氧化以形成用于电阻式开关存储元件的金属氧化物。 可以沉积多层导电材料，每层具有不同的氧化速率。 可以利用导电层的差异氧化速率来确保在制造期间形成所需厚度的金属氧化物层。

公开(公告)号：US20130071982A1

公开(公告)日：2013-03-21

申请号：US13675695

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Nitin Kumar ,  Tony P. Chiang ,  Chi-I Lang ,  Prashant B. Phatak ,  Jinhong Tong

IPC: H01L45/00

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US09761800B2

公开(公告)日：2017-09-12

申请号：US14312628

申请日：2014-06-23

Applicant: Intermolecular, Inc.

Inventor： Prashant B. Phatak ,  Ronald J. Kuse ,  Jinhong Tong

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.

公开(公告)号：US09178031B2

公开(公告)日：2015-11-03

申请号：US14300917

申请日：2014-06-10

Applicant: Intermolecular Inc.

Inventor： Jinhong Tong

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/51 ,  H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/28 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/512 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45553 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Abstract translation: 提供了用于形成涉及铒氧化物层沉积，接着氧化铪层沉积的栅极电介质的两步ALD沉积工艺。 氧化铪可以提供高介电常数，高密度，大带隙和良好的热稳定性。 铒氧化物可以作为阻止氧扩散的屏障，这可以导致增加栅极电介质的有效氧化物厚度并防止可能导致较高漏电流的铪硅反应。

公开(公告)号：US20150147865A1

公开(公告)日：2015-05-28

申请号：US14612897

申请日：2015-02-03

Applicant: Intermolecular, Inc.

Inventor： Ronald John Kuse ,  Tony Chiang ,  Michael Miller ,  Prashant Phatak ,  Jinhong Tong

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

Abstract translation: 描述了具有改进的开关特性的电阻式开关存储元件，包括具有第一电极和第二电极的存储元件，在第一电极和第二电极之间的开关层，开关层包括第一金属氧化物，第一带隙较大 所述开关层具有第一厚度，以及所述开关层和所述第二电极之间的耦合层，所述耦合层包括第二金属氧化物，所述第二金属氧化物具有大于所述第一带隙的第二带隙，所述耦合层具有 第二厚度小于第一厚度的25％。

公开(公告)号：US09023137B2

公开(公告)日：2015-05-05

申请号：US14013760

申请日：2013-08-29

Applicant: Intermolecular, Inc.

Inventor： Bob Kong ,  Igor Ivanov ,  Zhi-Wen Sun ,  Jinhong Tong

IPC: C23C18/44 ,  H01L21/02 ,  H01L21/033 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/768 ,  C23C18/18 ,  C23C18/16 ,  H01L27/105 ,  H01L49/02

CPC classification number: C23C18/44 ,  C23C18/1605 ,  C23C18/1607 ,  C23C18/1637 ,  C23C18/1844 ,  H01L21/02068 ,  H01L21/0332 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/1052 ,  H01L28/65 ,  Y10T428/12493 ,  Y10T428/12875 ,  Y10T428/12903 ,  Y10T428/24917

Abstract: Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices.

Abstract translation: 本发明的实施方案描述了使用自引发的无电镀方法在铂膜上选择性镀铂的方法。 特别地，铂膜被镀在厚度小于300埃的非常薄的铜膜上。 还描述了化学镀溶液和所得结构。 该方法在逻辑器件，存储器件和光伏器件的半导体处理中具有应用。

公开(公告)号：US20150001555A1

公开(公告)日：2015-01-01

申请号：US14488712

申请日：2014-09-17

Applicant: Intermolecular, Inc.

Inventor： Anh Duong ,  Tony Chiang ,  Zachary M. Fresco ,  Nitin Kumar ,  Chi-I Lang ,  Jinhong Tong ,  Anna Tsizelmon

IPC: H01L23/532

CPC classification number: H01L23/5329 ,  C09D129/04 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Abstract translation: 提出了修改图案化半导体衬底的方法，包括：提供包括电介质区域和导电区域的图案化半导体衬底表面; 以及将两亲表面改性剂施加到所述电介质区域以改变所述电介质区域。 在一些实施例中，修改电介质区域包括改变电介质区域的润湿角度。 在一些实施例中，改变润湿角度包括使介电区域的表面成为亲水性。 在一些实施方案中，方法还包括将水溶液施加到图案化的半导体衬底表面。 在一些实施例中，导电区域被水溶液选择性地增强。 在一些实施例中，方法还包括提供由低k电介质材料形成的电介质区域。 在一些实施方案中，施加两亲表面改性剂修饰低k电介质区域与随后工艺的相互作用。

公开(公告)号：US08889479B2

公开(公告)日：2014-11-18

申请号：US13675695

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Nitin Kumar ,  Tony P. Chiang ,  Chi-I Lang ,  Prashant B. Phatak ,  Jinhong Tong

IPC: H01L21/00 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US08575021B2

公开(公告)日：2013-11-05

申请号：US13829290

申请日：2013-03-14

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Anh Duong ,  Zachary Fresco ,  Nitin Kumar ,  Chi-I Lang ,  Sandra G. Malhotra ,  Jinhong Tong

IPC: H01L21/31 ,  H01L21/312 ,  H01L21/32

CPC classification number: H01L21/02112 ,  H01L21/02123 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/7685

Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract translation: 描述基板处理方法。 所述方法包括在基底上形成材料层。 所述方法包括选择分子屏蔽层（MML）的成分以消除作为衬底处理的结果的材料层中的变化的影响。 所述方法包括通过在材料层上选择性地沉积MML来使材料层的表面特性归一化。