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    Scalable production method for AAV
    2.
    发明授权
    Scalable production method for AAV 有权
    AAV可扩展生产方法

    公开(公告)号：US09198984B2

    公开(公告)日：2015-12-01

    申请号：US12226588

    申请日：2007-04-27

    Applicant: Martin Lock ,  Luc H Vandenberghe ,  James M. Wilson

    Inventor： Martin Lock ,  Luc H Vandenberghe ,  James M. Wilson

    IPC: A61K38/00 ,  C12N7/00 ,  A61K48/00 ,  C07K14/005

    CPC classification number: C12N7/00 ,  A61K48/0091 ,  C07K14/005 ,  C12N2750/14151

    Abstract: A method for producing AAV, without requiring cell lysis, is described. The method involves harvesting AAV from the supernatant. For AAV having capsids with a heparin binding site, the method involves modifying the AAV capsids and/or the culture conditions to ablate the binding between the AAV heparin binding site and the cells, thereby allowing the AAV to pass into the supernatant, i.e., media. Thus, the method of the invention provides supernatant containing high yields of AAV which have a higher degree of purity from cell membranes and intracellular materials, as compared to AAV produced using methods using a cell lysis step.

    Abstract translation: 描述了不需要细胞裂解的生产AAV的方法。 该方法包括从上清液中收获AAV。 对于具有肝素结合位点的衣壳的AAV，该方法包括修饰AAV衣壳和/或培养条件以消除AAV肝素结合位点与细胞之间的结合，从而允许AAV进入上清液，即培养基 。 因此，与使用细胞裂解步骤的方法产生的AAV相比，本发明的方法提供了含有高产率的AAV的上清液，其具有比细胞膜和细胞内物质更高的纯度。

    Dual operational mode CML latch
    10.
    发明授权
    Dual operational mode CML latch 失效
    双操作模式CML锁存器

    公开(公告)号：US07358787B2

    公开(公告)日：2008-04-15

    申请号：US11307923

    申请日：2006-02-28

    Applicant: Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

    Inventor： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

    IPC: H03K3/289

    CPC classification number: H03K3/356043

    Abstract: A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

    Abstract translation: 提供了一种双用途电流模式逻辑（“CML”）锁存电路，其包括可操作以接收至少一对差分输入数据信号和至少一个时钟信号的CML锁存器。 CML锁存器可操作以根据输入差分数据信号对的状态产生至少一个输出信号。 模式控制装置可操作以接收模式控制信号以将CML锁存器作为缓冲器或锁存器操作。 以这种方式，当模式控制信号无效时，CML锁存器产生并以由至少一个时钟信号确定的定时锁存输出信号，并且当模式控制信号有效时，CML锁存器产生输出信号，使得 每当差分输入数据信号对的状态改变时，输出信号就会改变。

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