公开(公告)号：US20250131965A1

公开(公告)日：2025-04-24

申请号：US19005835

申请日：2024-12-30

Applicant: Micron Technology, Inc.

Inventor： AbdelHakim S. Alhussien ,  James Fitzpatrick ,  Patrick Robert Khayat ,  Sivagnanam Parthasarathy

IPC: G11C16/26 ,  G11C11/56 ,  G11C29/50

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

公开(公告)号：US12266420B2

公开(公告)日：2025-04-01

申请号：US18509088

申请日：2023-11-14

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G11C7/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

公开(公告)号：US12223190B2

公开(公告)日：2025-02-11

申请号：US18370342

申请日：2023-09-19

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

公开(公告)号：US20240412795A1

公开(公告)日：2024-12-12

申请号：US18808566

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick Robert Khayat ,  AbdelHakim S. Alhussien

IPC: G11C29/12 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C29/14 ,  G11C29/44

Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.

公开(公告)号：US20240384168A1

公开(公告)日：2024-11-21

申请号：US18785912

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: C09K13/00 ,  C09K15/30 ,  G03F7/42

Abstract: Embodiments disclosed can include determining, for each wordline group of one or more wordline groups of the plurality of wordlines, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group; and responsive to determining that an aggregate read window budget (RWB) increase for the block satisfies a threshold range associated with a target RWB increase, modifying the parameter of the memory access operation according to the target adjustment, wherein the target RWB increase is determined using a different PV voltage offset for each respective programming level of the memory cell associated with the wordline of the wordline group.

公开(公告)号：US20240379172A1

公开(公告)日：2024-11-14

申请号：US18778823

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Patrick Robert Khayat ,  AbdelHakim S. Alhussien

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04

Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.

公开(公告)号：US12119062B2

公开(公告)日：2024-10-15

申请号：US17884113

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G11C16/08 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/08 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/0483

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. Embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. Embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. Embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.

公开(公告)号：US20240338146A1

公开(公告)日：2024-10-10

申请号：US18743629

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.

公开(公告)号：US12073899B2

公开(公告)日：2024-08-27

申请号：US17536462

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick Robert Khayat ,  AbdelHakim S. Alhussien

IPC: G11C29/12 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C29/14 ,  G11C29/44

CPC classification number: G11C29/12005 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C29/14 ,  G11C29/44

Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.

公开(公告)号：US20240256328A1

公开(公告)日：2024-08-01

申请号：US18419352

申请日：2024-01-22

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Sivagnanam Parthasarathy

IPC: G06F9/48

CPC classification number: G06F9/485

Abstract: Methods, systems, and apparatuses mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and current bit is selected. In response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion, it is determined that the current bit was flipped in a previous iteration. The flipping of the current bit is bypassed in response to determining the current bit was flipped in the previous iteration.