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公开(公告)号：JP2006202481A
公开(公告)日：2006-08-03
申请号：JP2006062241
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C29/34 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/12 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a solving means for authenticating the success/failure of a test mode. SOLUTION: This memory is provided with an array of memory cells each having two storage elements, a plurality of peripheral devices for writing data in the memory cells and reading data from the memory cells, a plurality of voltage sources for generating a plurality of supply voltages to be used by the array and the peripheral device in response to an external voltage, and a test mode logic for determining whether the memory is a test mode or not. The plurality of peripheral devices include latch circuits for latching data stored in the first group of a memory element in response to a first external signal, and write permission circuits for writing the latched data in the second group of the memory element in response to a second external signal. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种用于认证测试模式的成功/失败的解决方案。 解决方案：该存储器具有每个具有两个存储元件的存储单元阵列，用于在存储器单元中写入数据并从存储器单元读取数据的多个外围设备，用于产生多个存储单元的多个电压源 用于响应于外部电压由阵列和外围设备使用的电源电压以及用于确定存储器是否是测试模式的测试模式逻辑。 多个外围设备包括用于响应于第一外部信号锁存存储在存储器元件的第一组中的数据的锁存电路，以及用于响应于第二外部存储元件将锁存的数据写入存储器元件的第二组的写许可电路 外部信号。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006202480A
公开(公告)日：2006-08-03
申请号：JP2006062155
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To solve the problem that there is an adverse influence such as noise when maximum power is not necessary if a voltage pump of a size enough to supply necessary power is arranged. SOLUTION: A voltage pump for the dynamic random access memory is provided with a variable pump for supplying power at a variable level in response to a clock signal and an enable signal generated by the dynamic random access memory, an oscillator for generating the clock signal, and a regulator for generating a first signal to control the oscillator means. The variable pump includes a plurality of first independent pump circuits, and a plurality of second independent pump circuits. Each pump includes two substantially similar pump parts cooeperatively operated in response to the clock signal. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：为了解决如果排列足够大的电压的电压泵，则不需要最大功率时会产生诸如噪声等不良影响的问题。 解决方案：用于动态随机存取存储器的电压泵设置有可变泵，用于响应于由动态随机存取存储器产生的时钟信号和使能信号以可变电平提供功率;振荡器，用于产生 时钟信号和用于产生第一信号以调节振荡器装置的调节器。 可变泵包括多个第一独立泵回路和多个第二独立泵回路。 每个泵包括响应于时钟信号共同操作的两个基本相似的泵部件。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006202477A
公开(公告)日：2006-08-03
申请号：JP2006062026
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a means for supplying a proper operation voltage to a large semiconductor memory device. SOLUTION: A method for operating the amplification part of a voltage regulator for the dynamic random access memory includes a step of operating at least one power amplifier while a memory array is operated, a step of operating at least one booster amplifier independently of a power amplifier while a voltage pump is operated, and a step of operating a standby amplifier maintained at a low current level irrespective of the operated states of the power amplifier and the booster amplifier. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种用于向大型半导体存储器件提供适当的操作电压的装置。 解决方案：用于操作用于动态随机存取存储器的电压调节器的放大部分的方法包括在存储器阵列被操作时操作至少一个功率放大器的步骤，独立于存储器阵列操作至少一个升压放大器的步骤 功率放大器，同时操作电压泵;以及操作备用放大器的步骤，保持在低电流水平，而与功率放大器和升压放大器的操作状态无关。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006190469A
公开(公告)日：2006-07-20
申请号：JP2006062198
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To cope with a problem during power-up and to perform power-up surely in the shortest time. SOLUTION: The dynamic random access memory is provided with a memory cell array, a plurality of peripheral apparatus for writing data in the memory cell and reading out data from the memory cell, a plurality of voltage sources generating a plurality of supply voltages used by the array and the plurality of peripheral sources responding to the outside voltage, and a power-up sequence circuit for controlling power-up operation for a certain voltage source among a plurality of voltage sources. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：解决上电时的问题，并在最短的时间内确保上电。 解决方案：动态随机存取存储器设置有存储单元阵列，用于在存储单元中写入数据并从存储单元读出数据的多个外围设备，产生多个电源电压的多个电压源 由所述阵列和所述多个外围电源响应外部电压使用的上电序列电路，以及用于控制多个电压源中的某个电压源的上电操作的上电序列电路。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2007299522A
公开(公告)日：2007-11-15
申请号：JP2007174529
申请日：2007-07-02
Inventor： JANZEN JEFFERY W , MANNING TROY A , MARTIN CHRIS G , KEETH BRENT
IPC: G06F12/00 , G11C11/401 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/407 , G11C11/4072 , G11C11/4076 , G11C11/409
CPC classification number: G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
Abstract: PROBLEM TO BE SOLVED: To uniformize a system read latency of a memory device for the purpose of reducing complexity of a memory controller.
SOLUTION: By a control circuit 2000, after receiving the flag signal by the control circuit, a memory device begins to output data associated with a previously received command onto at least one data signal line from a memory array in the predetermined number of read clock cycles, and the aforementioned number of read clock cycles is preliminarily determined according to a feature of signal propagation in order to equalize it to the read latency of the memory device.
COPYRIGHT: (C)2008,JPO&INPITAbstract translation: 要解决的问题：为了降低存储器控制器的复杂性的目的，使存储器件的系统读取等待时间均匀化。 解决方案：通过控制电路2000，在由控制电路接收到标志信号之后，存储器件开始将与先前接收到的命令相关联的数据从预定数量的存储器阵列的存储器阵列输出到至少一个数据信号线上 读取时钟周期，并且根据信号传播的特征预先确定上述数量的读取时钟周期，以便将其与存储器件的读取等待时间相等。 版权所有（C）2008，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2006202485A
公开(公告)日：2006-08-03
申请号：JP2006065451
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L23/50 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To realize a high-density memory by an economical method. SOLUTION: This memory is provided with a plurality of memory cells, a plurality of pads, a plurality of peripheral devices for transmitting data between the plurality of memory cells and the plurality of pads, a plurality of voltage sources for supplying a plurality of supply voltages, a power distribution bus for supplying the plurality of supply voltages, and a package having a lead frame constituting a part of the power distribution bus to seal the memory. The lead frame constituting a part of the power distribution bus forms a ground bus. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：通过经济的方法实现高密度存储器。 解决方案：该存储器设置有多个存储器单元，多个焊盘，用于在多个存储单元和多个焊盘之间传输数据的多个外围设备，用于提供多个存储单元的多个电压源 的供电电压，用于提供多个电源电压的配电总线，以及具有构成配电总线的一部分的引线框的封装以密封存储器。 构成配电总线的一部分的引线框构成接地总线。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006244695A
公开(公告)日：2006-09-14
申请号：JP2006062110
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To obtain the optimal chip layout under restrictions in arranging pins and to provide power supply architecture in which a device can perform appropriate operation in the shortest period of time. SOLUTION: The power supply for a dynamic random access memory is equipped with multiple array blocks and multiple pads arranged in the center of the multiple array blocks, arranged near the multiple pads and equipped with multiple voltage source for generating the supply voltage to the multiple array blocks. The multiple voltage source is equipped with a voltage regulator having multiple power amplifiers, and at least one power amplifier is related with each of the multiple array blocks. In order to attain the setup output power level, the multiple voltage sources include voltage pumps having multiple voltage pump circuits divided into multiple groups for performing either of separate or simultaneous operation. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：为了在布置引脚的限制下获得最佳的芯片布局，并提供设备可以在最短的时间内执行适当的操作的电源架构。 解决方案：动态随机存取存储器的电源配备有多个阵列块和多个焊盘，布置在多个阵列块的中心，布置在多个焊盘附近，并配有多个电压源，用于产生电源电压 多个数组块。 多电压源配备有具有多个功率放大器的电压调节器，并且至少一个功率放大器与多个阵列块中的每一个相关联。 为了获得设定输出功率电平，多个电压源包括具有多个电压泵电路的电压泵，该电压泵电路被分成多组，用于执行单独或同时操作。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006202484A
公开(公告)日：2006-08-03
申请号：JP2006065222
申请日：2006-03-10
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C5/02 , G11C5/06 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/409 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To realize a high-density memory by an economical method. SOLUTION: This dynamic random memory is provided with a plurality of independent arrays constituted of memory cells and having digit lines extending therethrough, and a plurality of peripheral devices for writing/reading data in the memory cells. The peripheral device is provided with a plurality of sense amplifiers for sensing signals on the digit lines. The sense amplifier is provided with a plurality of peripheral devices controlled by a control signal larger than a data signal written in the memory cell, a power source for generating a plurality of supply voltages, and a power distribution bus for supplying the plurality of supply voltages to the plurality of independent arrays and the peripheral devices. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：通过经济的方法实现高密度存储器。 解决方案：该动态随机存储器设置有由存储单元构成的多个独立阵列，并且具有穿过其中的数字线，以及用于在存储单元中写入/读取数据的多个外围设备。 外围设备设置有用于感测数字线上的信号的多个读出放大器。 感测放大器设置有多个外围设备，其由大于写入存储单元中的数据信号的控制信号控制，用于产生多个电源电压的电源以及用于提供多个电源电压的配电总线 到多个独立阵列和外围设备。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006190468A
公开(公告)日：2006-07-20
申请号：JP2006062175
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To use overvoltage/undervoltage sensors to stabilize supply voltage of a large capacity memory. SOLUTION: The dynamic random access memory is provided with a memory cell array, a plurality of peripheral apparatus for writing data in the memory cell and reading out data from the memory cell, a plurality of voltage sources which are a plurality of voltage sources generating a plurality of supply voltages used by the array and the plurality of peripheral sources responding to the outside voltage and one of which comprises a voltage generator generating output voltage, a voltage detecting circuit generating the over-voltage signal and the under-voltage signal indicating whether the output voltage is within a first setting range or not responding to the output voltage, and a logic circuit for providing display of stability of the voltage generator responding to the over-voltage signal and the under-voltage signal. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：使用过电压/欠压传感器来稳定大容量存储器的电源电压。 解决方案：动态随机存取存储器设置有存储单元阵列，多个外围设备，用于在存储单元中写入数据并从存储单元中读出数据，多个电压源是多个电压 源产生阵列使用的多个电源电压和响应于外部电压的多个外围源，并且其中一个包括产生输出电压的电压发生器，产生过电压信号的电压检测电路和欠压信号 指示输出电压是否在第一设定范围内或者不响应于输出电压;以及逻辑电路，用于响应于过电压信号和欠压信号提供对电压发生器的稳定性的显示。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JP2006216228A
公开(公告)日：2006-08-17
申请号：JP2006062011
申请日：2006-03-08
Inventor： KEETH BRENT , BUNKER LAYNE G , DERNER SCOTT J , TAYLOR RONALD L , MULLIN JOHN S , BEFFA RAYMOND J , ROSS FRANK F , KINSMAN LARRY D
IPC: G11C11/401 , G11C11/407 , G06F1/26 , G11C5/02 , G11C5/06 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C29/04 , G11C29/14 , H01L21/8242 , H01L27/108
CPC classification number: G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a means for properly supplying power to a large-scale semiconductor memory device. SOLUTION: A voltage regulator for the dynamic random access memory is provided with a voltage reference circuit for generating a reference voltage, and a plurality of power amplifiers having gains larger than 1 for amplifying supply voltages to supply power to the dynamic random access memory and responding to the reference voltage, and a control circuit for generating a control signal to control the plurality of power amplifiers. The voltage regulator for the dynamic random access memory is further provided with a circuit for generating a reference voltage from a voltage supplied from the outside, an amplifier for amplifying the reference voltage by a gain larger than one unit to generate an internal supply voltage to be used by first and second buses, and a control logic for generating a control signal to control the amplifier. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种用于向大规模半导体存储器件正确供电的装置。 解决方案：用于动态随机存取存储器的电压调节器设置有用于产生参考电压的电压参考电路，以及具有大于1的增益的多个功率放大器，用于放大电源电压以向动态随机存取 存储器并响应于参考电压，以及用于产生控制信号以控制多个功率放大器的控制电路。 用于动态随机存取存储器的电压调节器还设置有用于从外部提供的电压产生参考电压的电路，放大器，用于通过大于一个单位的增益放大参考电压，以产生内部电源电压 由第一和第二总线使用，以及用于产生控制信号以控制放大器的控制逻辑。 版权所有（C）2006，JPO＆NCIPI
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