公开(公告)号：EP1803215A1

公开(公告)日：2007-07-04

申请号：EP05796154.2

申请日：2005-09-14

Applicant: MOTOROLA, INC.

Inventor： GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H03B21/00

CPC classification number: G06F1/025 ,  G06F2211/902

Abstract: A direct digital synthesizer (DDS) ( 300 ) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) ( 317 ). The DDS ( 300 ) includes one or more dither sources ( 307 ) and a random access memory (RAM) ( 305 ). The RAM ( 305 ) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source ( 307 ) to compensate unequal unit delay values in the DTC ( 317 ).

公开(公告)号：EP0587792B1

公开(公告)日：1998-09-09

申请号：EP92913963.2

申请日：1992-06-02

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  SHARP, Ronald, E. ,  YESTER, Francis, R.

IPC: H04B1/16 ,  H04Q7/32

CPC classification number: H04B1/1027 ,  H04B1/1615 ,  H04L1/20 ,  H04W52/0238 ,  Y02D70/40

Abstract: A communication device 200 capable of operating in a communication system 100 having a control system which generates information signals with redundant information is disclosed. The communication device comprises: a receiver 214 for receiving the information signals; a circuit which can determine the signal quality of the received information signals 234; and a controller 226 which decodes the received information signals, and further compares the signal quality of the information signals with a predetermined value, and decides if the received signal quality is at least equal to the predetermined value in order to only decode a portion of the information signal. Upon the communication device decoding a portion of the information signal, the communication device 200 is placed in a battery saving mode in order to conserve battery life.

Abstract translation: 公开了能够在具有生成具有冗余信息的信息信号的控制系统的通信系统100中进行操作的通信装置200。 通信设备包括：接收器214，用于接收信息信号; 可以确定接收到的信息信号234的信号质量的电路; 以及对接收到的信息信号进行解码的控制器226，并且将信息信号的信号质量与预定值进行比较，并且确定接收到的信号质量是否至少等于预定值，以便仅解码部分 信息信号。 在通信设备对信息信号的一部分进行解码时，通信设备200被置于电池节电模式以便节省电池寿命。

公开(公告)号：WO2007104010A2

公开(公告)日：2007-09-13

申请号：PCT/US2007/063565

申请日：2007-03-08

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H03H11/26

CPC classification number: H03H11/265 ,  H03K5/131 ,  H03K2005/00065 ,  H03L7/1806

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract translation: 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。

公开(公告)号：WO2005072298A2

公开(公告)日：2005-08-11

申请号：PCT/US2005/002138

申请日：2005-01-25

Applicant: MOTOROLA, INC. ,  TOMERLIN, Andrew, T. ,  STENGEL, Robert, E.

Inventor： TOMERLIN, Andrew, T. ,  STENGEL, Robert, E.

IPC: H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/0802 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/16

Abstract: A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18,…, 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract translation: 与某些实施例一致的可配置电路具有可变长度延迟线（10），延迟线（10）具有输入（24）并且具有N个延迟元件（12,14,16,18，...，20） 提供多个N个延迟输出（T（0）至T（N））。 可变长度延迟线（10）还具有由程序命令确定的多个有效延迟元件。 可配置处理阵列（32）从主动延迟元件和辅助数据（38）接收延迟的输出。 可配置处理阵列具有可配置电路元件（104,130,150）的阵列。 可配置处理阵列被配置为以将要使用本发明的方式处理延迟的输出和辅助数据（38）。 该摘要不被认为是限制性的，因为其它实施例可能偏离本摘要中描述的特征。

公开(公告)号：WO2004095458A2

公开(公告)日：2004-11-04

申请号：PCT/US2004/011439

申请日：2004-04-14

Applicant: MOTOROLA, INC. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: G11C

CPC classification number: G06F1/025 ,  G06F2211/902

Abstract: A direct digital synthesizer (30) with noise shaping circuitry can comprise a ROM-less direct digital synthesizer having a quantizer (40) and a noise shaping loop incorporating the quantizer for shaping a quantization noise due to noise from the quantizer. The noise shaping loop can comprise a noise shaping filter (44) and the noise shaping loop can feed back to the noise shaping filter a difference between an input signal (49) to the quantizer and an output signal (43) from the quantizer. The ROM-less direct digital synthesizer can further include a dither (39) combined at an input of the quantizer.

Abstract translation: 具有噪声整形电路的直接数字合成器（30）可以包括具有量化器（40）的无ROM直接数字合成器和包含量化器的噪声整形环路，用于对来自量化器的噪声造成的量化噪声进行整形。 噪声整形环路可以包括噪声整形滤波器（44），并且噪声整形环路可以将与量化器的输入信号（49）和来自量化器的输出信号（43）之间的差值反馈给噪声整形滤波器。 无ROM直接数字合成器还可以包括在量化器的输入处组合的抖动（39）。

公开(公告)号：WO2003063435A1

公开(公告)日：2003-07-31

申请号：PCT/US2003/001304

申请日：2003-01-15

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  HECK, Joseph, P. ,  BOCKELMAN, David, E.

IPC: H04L25/00

CPC classification number: H03L7/0812 ,  H03K7/04 ,  H03K2005/00019 ,  H03L7/16 ,  H04L27/0008

Abstract: A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.

Abstract translation: 一种产生多个输出的延迟锁定环路（200）。 单个延迟线（24）在多个抽头选择电路（256A，265B，265C）之间共享。 可以在多个输出之间引入固定相移（412）。 调制信号可用于抽头选择处理以产生数字幅度，频率和/或相位调制。

公开(公告)号：EP1886405A2

公开(公告)日：2008-02-13

申请号：EP06751656.7

申请日：2006-04-27

Applicant: Motorola, Inc.

Inventor： THOMPSON, Bruce, M. ,  STENGEL, Robert, E.

IPC: H03F3/60

CPC classification number: H03F3/605

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections (102, 104, 106, and 108) and a plurality of drivers (110, 112, 114, and 116). Each of the plurality of drivers receives a common transmit signal (118) and an individual control signal (120, 122, 124, and 126). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal (128, 130, 132, and 134) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

公开(公告)号：EP1444783B1

公开(公告)日：2006-12-27

申请号：EP02773869.9

申请日：2002-10-23

Applicant: MOTOROLA, INC.

Inventor： JUAN, Jui-Kuo ,  STENGEL, Robert, E. ,  MARTIN, Frederick, L. ,  BOCKELMAN, David, E.

IPC: H03L7/07 ,  H03L7/081 ,  H03L7/16 ,  H03H11/26

CPC classification number: H03L7/16 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/14 ,  H03L2207/08

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

公开(公告)号：WO2004095191A2

公开(公告)日：2004-11-04

申请号：PCT/US2004/012139

申请日：2004-04-20

Applicant: MOTOROLA, INC. ,  TOMERLIN, Andrew ,  CAFARO, Nicholas, Giovanni ,  STENGEL, Robert, E.

Inventor： TOMERLIN, Andrew ,  CAFARO, Nicholas, Giovanni ,  STENGEL, Robert, E.

IPC: G06F

CPC classification number: G06F15/7867 ,  G06F1/08 ,  Y02D10/12 ,  Y02D10/13

Abstract: A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks, wherein certain of the configurable circuit blocks comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor (218) configures a function of a plurality of the configurable circuit blocks. A memory (224) stores program instructions used by the control processor (218). A multiple frequency generator (212) receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (218). A timing control circuit (236) receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit (236) operates under control of the control processor (218).

Abstract translation: 与本发明的某些实施例一致的可重构处理器电路（200）具有可配置电路块的阵列，其中某些可配置电路块包括可配置的算术逻辑单元和时钟数字逻辑电路之一。 控制处理器（218）配置多个可配置电路块的功能。 存储器（224）存储由控制处理器（218）使用的程序指令。 多频发生器（212）接收参考时钟并从其合成多个时钟信号，每个时钟信号由控制处理器（218）频率配置。 定时控制电路（236）接收多个时钟信号，在多个电路块中分配不同频率的多个时钟信号，并将时钟信号发送到电路块，其中定时控制电路（236）在控制下工作 的控制处理器（218）。

公开(公告)号：WO2003052992A2

公开(公告)日：2003-06-26

申请号：PCT/US2002/039319

申请日：2002-12-10

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  OLSON, Scott, A.

IPC: H04L

CPC classification number: H03F1/3223

Abstract: A feedforward amplifier and notch filter (150) according to the present invention uses a direct coupling of an amplifier stage (158) with the amplifier's load (RL). The main amplifier (202) is coupled through a transmission line (210) to the load. This direct coupled amplifier stage (158) is driven by an signal that induces a very low impedance in parallel with the load at the receive frequency, but appears as an open circuit at the desired frequencies so that the desired signal from the main amplifier is virtually unaffected while output components at the receive frequency are cancelled.

Abstract translation: 根据本发明的前馈放大器和陷波滤波器（150）使用放大器级（158）与放大器负载（RL）的直接耦合。 主放大器（202）通过传输线（210）耦合到负载。 该直接耦合放大器级158由一个信号驱动，该信号在接收频率处引起与负载并联的非常低的阻抗，但是以期望的频率显现为开路，使得来自主放大器的期望信号实际上 不受影响，而接收频率的输出组件被取消。