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公开(公告)号：JP2012231491A
公开(公告)日：2012-11-22
申请号：JP2012134942
申请日：2012-06-14
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： BLACK PETER J , NAGABHUSHANA SINDHUSHAYANA , CHALLA RAGHU , KEVIN SELTMANN
CPC classification number: H03G3/3036 , H03G3/3068
Abstract: PROBLEM TO BE SOLVED: To provide a communications device that can be supported with a simple calibration procedure that can not only support different operating frequencies and temperatures, but can also support multi-media modes of operation.SOLUTION: Systems and techniques for gain control include: amplifying a signal with an amplifier having a gain represented by one of a plurality of gain curves depending on a value of a parameter, the signal being amplified at a first one of the parameter values; and controlling the gain of the amplified signal from a predetermined gain curve relating to the gain curve of the amplifier for a second one of the parameter values by adjusting a gain control signal corresponding to a point on the predetermined gain curve as a function of the first one of the parameter values, and by applying the adjusted gain control signal to the amplifier.
Abstract translation: 要解决的问题：提供可以通过简单的校准程序来支持的通信设备，其不仅能够支持不同的工作频率和温度，而且还可以支持多媒体操作模式。 解决方案：用于增益控制的系统和技术包括：根据参数的值，放大具有由多个增益曲线之一表示的增益的放大器的信号，该信号在参数的第一个被放大 值; 以及通过调整对应于预定增益曲线上的点的增益控制信号，作为第一个参数值的函数，从与放大器对于第二参数值的增益曲线相关的预定增益曲线来控制放大信号的增益 参数值之一，并通过将调整后的增益控制信号应用于放大器。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2010213310A
公开(公告)日：2010-09-24
申请号：JP2010094023
申请日：2010-04-15
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide an architecture of a direct down conversion receiver capable of providing required signal gain and DC offset correction. SOLUTION: The architecture has a DC loop for removing DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing a gain control relating to the DVGA and an RF/analog circuit, and a serial bus interface (SBI) unit for providing control to the RF/analog circuit via a serial bus. Since these two loops perform mutual interaction with each other in design and disposition of the DVGA, an operation mode of the VGA loop is selected based on an operation mode of the DC loop. Within a time period while the DC loop is operating by a capturing mode, selection is made so as to be operated in inverse proportion to a bandwidth of the DC loop in the capturing mode. The control relating to some or all of RF/analog circuits is provided via the serial bus. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机的架构。 解决方案：该架构具有用于从信号分量中去除DC偏移的直流回路，用于提供增益范围的数字可变增益放大器（DVGA），用于执行与增益范围相关的增益控制的自动增益控制（AGC） DVGA和RF /模拟电路以及串行总线接口（SBI）单元，用于通过串行总线向RF /模拟电路提供控制。 由于这两个循环在DVGA的设计和配置中彼此相互作用，所以基于DC循环的操作模式来选择VGA循环的操作模式。 在DC循环通过捕获模式操作的时间段内，选择在捕获模式中与DC环路的带宽成反比地运行。 通过串行总线提供与RF /模拟电路中的一些或全部相关的控制。 版权所有（C）2010，JPO＆INPIT
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3.发明专利
公开(公告)号：JP2009284498A
公开(公告)日：2009-12-03
申请号：JP2009157265
申请日：2009-07-01
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： CHALLA RAGHU , KASTURI NITIN , SCHLEGEL NIKOLAI
CPC classification number: G06F7/5235 , G06F1/0307 , G06F7/483 , G06F7/556
Abstract: PROBLEM TO BE SOLVED: To provide a simplified VGA configuration using the fact that multiplication within a normal numerical domain can be performed by addition within a logarithmic domain.
SOLUTION: The digital voltage gain amplifier (digital VGA) 132 operates within the logarithmic domain. Properties of the logarithmic domain are exploited to replace the complex multiplier of a conventional VGA 132 with a simple and relatively inexpensive adder 306. Additional techniques are described to significantly reduce the size of one or more lookup-tables LUTs implemented within the digital VGA 132. In this manner, a much more simple, lower-cost design of a digital VGA is achieved.
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：为了提供简化的VGA配置，使用在正常数值域内的乘法可以通过在对数域内加法来执行的事实。 解决方案：数字电压增益放大器（数字VGA）132在对数域内运行。 利用对数域的属性用简单且相对便宜的加法器306代替常规VGA 132的复数乘法器。描述了附加技术以显着减小在数字VGA 132内实现的一个或多个查找表LUT的大小。 以这种方式，实现了数字VGA的更简单，更低成本的设计。 版权所有（C）2010，JPO＆INPIT
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4.发明专利
公开(公告)号：JP2012165428A
公开(公告)日：2012-08-30
申请号：JP2012080737
申请日：2012-03-30
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： CHALLA RAGHU , BARTHIS AWKWARD , HUGHES ROBBIN D
CPC classification number: H04B1/70756 , H04B2201/70709 , H04W52/0216 , H04W52/029 , H04W56/0035 , Y02D70/00 , Y02D70/40
Abstract: PROBLEM TO BE SOLVED: To provide a device to facilitate efficient use with a low frequency and low power for a sleep mode even when relatively large slot cycles are defined in a slotted paging system.SOLUTION: The technique includes reducing power in a wireless communication device for a first sleep period and then increasing power in the wireless communication device for an intermediate wake period after the first sleep period to estimate an error of a sleep clock. The method further includes reducing power in the wireless communication device for a second sleep period after the intermediate wake period. An intermediate wake mode implemented during the intermediate period can be used to estimate an error of a sleep mode without performing one or more tasks associated with an awake mode, such as demodulation.
Abstract translation: 要解决的问题：即使在时隙寻呼系统中定义相对大的时隙周期，提供一种用于便于睡眠模式的低频和低功率有效使用的设备。 解决方案：该技术包括在第一睡眠周期内减少无线通信设备中的功率，然后在第一睡眠周期之后的中间唤醒周期增加无线通信设备中的功率，以估计睡眠时钟的误差。 该方法还包括在中间唤醒周期之后的第二睡眠时段中减少无线通信设备中的功率。 在中间周期期间实现的中间唤醒模式可以用于估计睡眠模式的错误，而不执行与诸如解调之类的唤醒模式相关联的一个或多个任务。 版权所有（C）2012，JPO＆INPIT
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公开(公告)号：JP2009010959A
公开(公告)日：2009-01-15
申请号：JP2008177384
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture capable of providing the required signal gain and DC offset correction. SOLUTION: A direct downconversion receiver architecture has a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提供所需信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收器架构具有DC环路，用于消除信号分量的DC偏移，提供一系列增益的数字可变增益放大器（DVGA），提供增益控制的自动增益控制（AGC）回路 用于DVGA和RF /模拟电路，以及串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。 版权所有（C）2009，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2012070436A
公开(公告)日：2012-04-05
申请号：JP2011270605
申请日：2011-12-09
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： SIMIC EMILIJA M , PATRICK CHRISTOPHER , CHALLA RAGHU , ROWITCH DOUGLAS N
CPC classification number: G01S19/235 , H04B1/26
Abstract: PROBLEM TO BE SOLVED: To provide systems, methods and apparatus for frequency control.SOLUTION: A receiver according to one embodiment includes a frequency control unit configured to receive a stream of samples including a plurality of received instances of a transmitted signal. The frequency control unit is configured to output a first correction signal (e.g. indicating a rotation) that is based on more than one of the received instances and a second correction signal (e.g. to control an oscillator) that is also based on more than one of the received instances. In some embodiments, a controlled oscillator is used to receive and/or transmit another signal, such as a signal received from a GPS space vehicle. In other embodiments, the received instances are from a GPS signal. In further embodiments, a fixed-frequency oscillator is used, and the second correction signal is used to receive and/or transmit another signal, such as a GPS signal.
Abstract translation: 要解决的问题：提供用于频率控制的系统，方法和装置。 解决方案：根据一个实施例的接收机包括频率控制单元，其被配置为接收包括发送信号的多个接收的实例的样本流。 频率控制单元被配置为输出基于多于一个接收到的实例的第一校正信号（例如指示旋转）和还基于多个接收实例中的多于一个的第二校正信号（例如，以控制振荡器） 接收的实例。 在一些实施例中，受控振荡器用于接收和/或发送另一信号，例如从GPS空中交通工具接收的信号。 在其他实施例中，所接收的实例来自GPS信号。 在另外的实施例中，使用固定频率振荡器，并且第二校正信号用于接收和/或发送诸如GPS信号的另一信号。 版权所有（C）2012，JPO＆INPIT
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公开(公告)号：JP2012065358A
公开(公告)日：2012-03-29
申请号：JP2011270606
申请日：2011-12-09
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： SIMIC EMILIJA M , PATRICK CHRISTOPHER , CHALLA RAGHU , ROWITCH DOUGLAS N
CPC classification number: G01S19/235 , H04B1/26
Abstract: PROBLEM TO BE SOLVED: To provide systems, methods, and apparatus for a frequency control.SOLUTION: A receiver according to one embodiment includes a frequency control unit configured to receive a stream of samples including a plurality of received instances of a transmitted signal. The frequency control unit is configured to output a first correction signal (e.g. indicating a rotation) that is based on more than one of the received instances and a second correction signal (e.g. to control an oscillator) that is also based on more than one of the received instances. In some embodiments, a controlled oscillator is used to receive and/or transmit another signal, such as a signal received from a GPS space vehicle. In other embodiments, the received instances are from a GPS signal. In further embodiments, a fixed-frequency oscillator is used, and the second correction signal is used to receive and/or transmit another signal, such as a GPS signal.
Abstract translation: 要解决的问题：提供用于频率控制的系统，方法和装置。 解决方案：根据一个实施例的接收机包括频率控制单元，其被配置为接收包括发送信号的多个接收的实例的样本流。 频率控制单元被配置为输出基于多于一个接收到的实例的第一校正信号（例如指示旋转）和还基于多个接收实例中的多于一个的第二校正信号（例如，以控制振荡器） 接收的实例。 在一些实施例中，受控振荡器用于接收和/或发送另一信号，例如从GPS空中交通工具接收的信号。 在其他实施例中，所接收的实例来自GPS信号。 在另外的实施例中，使用固定频率振荡器，并且第二校正信号用于接收和/或发送诸如GPS信号的另一信号。 版权所有（C）2012，JPO＆INPIT
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公开(公告)号：JP2008295076A
公开(公告)日：2008-12-04
申请号：JP2008177383
申请日：2008-07-07
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To obtain a direct down converting receiver architecture having a DC loop for removing a DC offset from a signal component, a digital variable gain amplifier (DVGA) for providing a gain range, an automatic gain control (AGC) loop for performing gain control relating to the DVGA and RF/analog circuits, and a serial bus interface (SBI) unit for providing control relating to the RF/analog circuits via a serial bus. SOLUTION: The DVGA is to be effectively designed and disposed. Since these two loops mutually performs interaction, an operation mode of the VGA loop is to be selected based on an operation mode of the DC loop. Selection is made so as to be in inverse proportion to bandwidth of the DC loop in a captured mode while the DC loop is operated by the captured mode. Control is to be provided to some or all of the RF/analog circuits via the serial bus. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：为了获得具有用于从信号分量中去除DC偏移的DC回路的直接下变频接收机架构，用于提供增益范围的数字可变增益放大器（DVGA），自动增益控制（AGC） ）环路，用于执行与DVGA和RF /模拟电路相关的增益控制;以及串行总线接口（SBI）单元，用于经由串行总线提供与RF /模拟电路相关的控制。
解决方案：DVGA要有效设计和处理。 由于这两个环路相互进行交互，所以基于DC循环的操作模式来选择VGA环路的操作模式。 在捕捉模式下，直流环路被捕捉模式操作时，进行与直流回路的带宽成反比例的选择。 将通过串行总线向部分或全部RF /模拟电路提供控制。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2013081184A
公开(公告)日：2013-05-02
申请号：JP2012243898
申请日：2012-11-05
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： CHALLA RAGHU , NITIN KASTURI , SCHLEGEL NIKOLAI
IPC: G06F1/00 , H03G3/02 , G06F1/03 , G06F7/52 , G06F7/556 , H03G3/20 , H03G3/30 , H04B1/16 , H04B1/707
CPC classification number: G06F7/5235 , G06F1/0307 , G06F7/483 , G06F7/556
Abstract: PROBLEM TO BE SOLVED: To realize a simple and low-cost digital voltage gain amplifier.SOLUTION: A digital voltage gain amplifier includes: a logarithmic conversion unit that converts a baseband signal from a linear domain to a logarithmic domain; and an adder that adds the converted baseband signal to a gain signal to produce a scaled baseband signal. In addition, the digital voltage gain amplifier includes an exponential conversion unit that converts the scaled baseband signal from the logarithmic domain to the linear domain.
Abstract translation: 要解决的问题：实现一个简单而低成本的数字电压增益放大器。 数字电压增益放大器包括：对数转换单元，其将基带信号从线性域转换成对数域; 以及将转换后的基带信号与增益信号相加以产生缩放的基带信号的加法器。 此外，数字电压增益放大器包括一个指数变换单元，它将经缩放的对数域的基带信号转换成线性域。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2010193489A
公开(公告)日：2010-09-02
申请号：JP2010085217
申请日：2010-04-01
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INJUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
CPC classification number: H03G3/3078 , H03G3/3068 , H03G3/3089
Abstract: PROBLEM TO BE SOLVED: To provide a direct downconversion receiver architecture providing a signal gain and DC offset correction. SOLUTION: The direct downconversion receiver architecture includes: a DC loop to remove DC offset from signal components; a digital variable gain amplifier (DVGA) to provide a range of gains; an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry; and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The operating mode of the VGA loop is selected based on the operating mode of the DC loop, since these two loops interact with each other. The duration of time the DC loop is operated in an acquisition mode is selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种提供信号增益和DC偏移校正的直接下变频接收机架构。 解决方案：直接下变频接收机架构包括：DC信号消除DC偏移的DC环路; 数字可变增益放大器（DVGA）提供一系列增益; 自动增益控制（AGC）回路，为DVGA和RF /模拟电路提供增益控制; 以及串行总线接口（SBI）单元，通过串行总线提供对RF /模拟电路的控制。 基于DC环路的工作模式选择VGA环路的工作模式，因为这两个环路相互交互。 在采集模式下，DC环路工作的持续时间被选择为与采集模式中的DC环路带宽成反比。 版权所有（C）2010，JPO＆INPIT
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