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    System and method for implementing cyclic redundancy check
    1.
    发明专利
    System and method for implementing cyclic redundancy check 有权
    用于实施循环冗余检查的系统和方法

    公开(公告)号：JP2011083006A

    公开(公告)日：2011-04-21

    申请号：JP2010253017

    申请日：2010-11-11

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： STEELE BRIAN ,  WILEY GEORGE A

    IPC: H04L1/00

    CPC classification number: H04L7/10 ,  G09G5/006 ,  G09G2370/045 ,  G09G2370/10 ,  H04L7/048

    Abstract: PROBLEM TO BE SOLVED: To provide systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information.
    SOLUTION: There is provided a cyclic redundancy check (CRC) checker that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator 910, a CRC corrupter 920, an error detector 930 and an error value generator 940.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于实现循环冗余检查以改善链路初始化处理和交换系统错误信息的系统和方法。 提供了包括唯一模式检测器，CRC发生器，CRC初始化器和CRC校验器的循环冗余校验（CRC）检查器。 CRC校验器预先为CRC生成器提供了一个独特的模式。 在接收到通过数字传输链路接收的数据流中的唯一模式之后，CRC检查器继续检查CRC，而不需要排队和存储数据。 在另一方面，提供了一种CRC发生器系统，其有意地破坏CRC值以传输系统错误信息。 CRC发生器系统包括CRC发生器910，CRC腐蚀器920，误差检测器930和误差值发生器940.版权所有（C）2011，JPO＆INPIT

    Method and system for updating buffer
    2.
    发明专利
    Method and system for updating buffer 有权
    用于更新缓冲器的方法和系统

    公开(公告)号：JP2011041290A

    公开(公告)日：2011-02-24

    申请号：JP2010196663

    申请日：2010-09-02

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： WILEY GEORGE A ,  STEELE BRIAN

    IPC: H04L13/08

    CPC classification number: G09G5/006 ,  G09G5/393 ,  H04J3/047 ,  H04W88/02

    Abstract: PROBLEM TO BE SOLVED: To provide methods and systems for updating a buffer. SOLUTION: The present invention provides a method for updating a buffer, the method including: strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost and space savings compared to conventional buffering approaches. The method also prevents image tearing when used to update a frame buffer associated with a display, but is not limited to such applications. The present invention provides efficient mechanisms to enable buffer update across a communication link. The present invention provides a method for relaying timing information across a communication link. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供更新缓冲区的方法和系统。 解决方案：本发明提供了一种用于更新缓冲器的方法，该方法包括：策略性地写入缓冲器以实现对缓冲器的并发读取和写入。 该方法消除了对双缓冲的需要，从而与常规缓冲方法相比，导致实现成本和空间节省。 当用于更新与显示器相关联的帧缓冲器时，该方法还防止图像撕裂，但不限于此类应用。 本发明提供了有效的机制来实现通过通信链路的缓冲器更新。 本发明提供一种用于在通信链路上中继定时信息的方法。 版权所有（C）2011，JPO＆INPIT

    High data rate interface with improved link synchronization
    3.
    发明专利
    High data rate interface with improved link synchronization 有权
    具有改进的链路同步的高数据速率接口

    公开(公告)号：JP2010183593A

    公开(公告)日：2010-08-19

    申请号：JP2010053143

    申请日：2010-03-10

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： ANDERSON JON JAMES ,  STEELE BRIAN ,  WILEY GEORGE A ,  SHEKHAR SHASHANK

    IPC: H04L29/06 ,  G06F15/16 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04M1/725 ,  H04W80/02 ,  H04W84/10 ,  H04W92/08

    CPC classification number: H04L65/1069 ,  H04L12/40071 ,  H04L12/40117 ,  H04L29/06027 ,  H04L65/4069 ,  H04L65/80 ,  H04L69/18 ,  H04L69/22 ,  H04M1/72527 ,  H04W56/00 ,  Y02D70/12 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: PROBLEM TO BE SOLVED: To transfer digital presentation data at high speed between a host device and a client device. SOLUTION: The present invention relates to a data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. The signal protocol is used by link controllers configured to generate, transmit and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low-power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：在主机设备和客户端设备之间高速传输数字呈现数据。 解决方案：本发明涉及一种数据接口，用于通过链路连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成通信协议，用于传送预先选择的一组数字控制数据和数字 演示数据。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到客户端 通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效的低功耗双向高速数据传输机制。 版权所有（C）2010，JPO＆INPIT

    High data rate interface
    6.
    发明专利
    High data rate interface 有权
    高数据速率接口

    公开(公告)号：JP2010011480A

    公开(公告)日：2010-01-14

    申请号：JP2009209851

    申请日：2009-09-10

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： ANDERSON JON JAMES ,  STEELE BRIAN ,  WILEY GEORGE A ,  SHEKHAR SHASHANK

    IPC: H04L29/06 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L12/64 ,  H04L29/08 ,  H04M1/725

    CPC classification number: H04L12/40052 ,  H04L47/283 ,  H04L65/608 ,  H04L69/03 ,  H04L69/10 ,  H04L69/18 ,  H04L69/323 ,  H04L69/324 ,  H04M1/72527 ,  Y02D70/12 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: PROBLEM TO BE SOLVED: To provide a data digital interface for transferring digital data between a host device and a client device at high speed. SOLUTION: A data interface is for transferring the digital data between a host 202 and a client 204 over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. A signal protocol is used by link controllers which are configured to generate, transmit, and receive a packet forming the communication protocol and to form the digital data into one or more types of data packets. At least one link controller resides always at the host device. The link controllers are coupled to the client 204 through the communication path, The interface provides a cost-effective, low power, bi-directional, and high-speed data transfer mechanism over a short-range "serial" type data link. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在主机设备和客户端设备之间高速传输数字数据的数据数字接口。 解决方案：数据接口用于通过链路连接在一起的分组结构通过通信路径在主机202和客户端204之间传送数字数据，以形成通信协议，用于传送预先选择的一组数字控制数据和数字呈现 数据。 链路控制器使用信号协议，链路控制器被配置为生成，发送和接收形成通信协议的分组，并将数字数据形成为一种或多种类型的数据分组。 至少一个链路控制器始终位于主机设备上。 链路控制器通过通信路径耦合到客户端204.该接口通过短距离“串行”类型数据链路提供了具有成本效益的低功率，双向和高速数据传输机制。 版权所有（C）2010，JPO＆INPIT

    Double data rate serial encoder
    7.
    发明专利
    Double data rate serial encoder 有权
    双数据速率串行编码器

    公开(公告)号：JP2012165388A

    公开(公告)日：2012-08-30

    申请号：JP2012040094

    申请日：2012-02-27

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： STEELE BRIAN ,  WILEY GEORGE A ,  MUSFELDT CURTIS

    IPC: H03M9/00

    CPC classification number: G09G5/006 ,  G09G5/393 ,  H04J3/047 ,  H04W88/02

    Abstract: PROBLEM TO BE SOLVED: To provide a double data rate serial encoder.SOLUTION: The serial encoder comprises: a multiplexer 508 having a plurality of inputs; a plurality of latches 502 having a plurality of data inputs and coupled to the inputs of the multiplexer; an enabler 504 which is coupled to the latches and enables the latches to update their data inputs; and a counter 506 which is coupled to the multiplexer and selects one of the inputs of the multiplexer for output. In addition, the multiplexer outputs a glitch-less data signal during input transitions. The multiplexer includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence outputted by the counter.

    Abstract translation: 要解决的问题：提供双数据速率串行编码器。 串行编码器包括：具有多个输入的多路复用器508; 具有多个数据输入并耦合到多路复用器的输入端的多个锁存器502; 启动器504，其耦合到锁存器并使锁存器能够更新其数据输入; 以及计数器506，其耦合到多路复用器并选择多路复用器的输入之一用于输出。 此外，多路复用器在输入转换期间输出无毛刺数据信号。 复用器包括基于由计数器输出的输入选择序列的先验知识而优化的输出选择算法。 版权所有（C）2012，JPO＆INPIT

    High-speed data rate interface device and method
    9.
    发明专利
    High-speed data rate interface device and method 有权
    高速数据速率接口设备和方法

    公开(公告)号：JP2010213299A

    公开(公告)日：2010-09-24

    申请号：JP2010089292

    申请日：2010-04-08

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： ANDERSON JON JAMES ,  STEELE BRIAN ,  WILEY GEORGE A ,  SHEKHAR SHASHANK

    IPC: H04L29/08 ,  H04J3/00 ,  H04J3/24 ,  H04L12/28 ,  H04L12/56 ,  H04L12/64 ,  H04L29/06 ,  H04M1/725

    CPC classification number: H04L12/6418 ,  H04L29/06027 ,  H04L65/1069 ,  H04L65/4069 ,  H04L65/80 ,  H04L67/125 ,  H04L67/36 ,  H04L69/329 ,  H04L2012/6483 ,  H04M1/72527 ,  Y02D70/144 ,  Y02D70/26

    Abstract: PROBLEM TO BE SOLVED: To provide a data interface capable of transferring digital data between a host device and a client device over a communication path using a packet structure linked to both, in order to form a communication protocol for communicating a preselected set of digital control data and digital presentation data. SOLUTION: A signal protocol is configured to generate, transmit, and receive a packet forming a communication protocol and form digital data into a data packet of one or more types. At least one set of the signal protocol resides at the host device, and is used by a link controller coupled to the client device through the communication path. The interface is a highly cost effective and low power consumption bidirectional high speed data transfer mechanism over a short range "serial" type data link. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够通过使用与两者相关联的分组结构的通信路径在主机设备和客户端设备之间传送数字数据的数据接口，以便形成用于通信预选集合的通信协议 的数字控制数据和数字显示数据。 解决方案：信号协议被配置为生成，发送和接收形成通信协议的分组，并将数字数据形成为一种或多种类型的数据分组。 至少一组信号协议驻留在主机设备处，并且由通过通信路径耦合到客户端设备的链路控制器使用。 该接口是一种在短距离“串行”类型数据链路上的高性价比和低功耗双向高速数据传输机制。 版权所有（C）2010，JPO＆INPIT

    High data rate interface
    10.
    发明专利
    High data rate interface 审中-公开
    高数据速率接口

    公开(公告)号：JP2012227933A

    公开(公告)日：2012-11-15

    申请号：JP2012116918

    申请日：2012-05-22

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： ANDERSON JON JAMES ,  STEELE BRIAN ,  WILEY GEORGE A ,  SHEKHAR SHASHANK

    IPC: H04L29/06 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L12/64 ,  H04L29/08 ,  H04M1/725 ,  H04N7/173

    CPC classification number: H04L12/40052 ,  H04L47/283 ,  H04L65/608 ,  H04L69/03 ,  H04L69/10 ,  H04L69/18 ,  H04L69/323 ,  H04L69/324 ,  H04M1/72527 ,  Y02D70/12 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: PROBLEM TO BE SOLVED: To provide a high data rate interface.SOLUTION: Provided is a data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control data and digital presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link.

    Abstract translation: 要解决的问题：提供高数据速率接口。 解决方案：提供了一种数据接口，用于通过链路连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制数据和数字呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并被耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型的数据链路提供了具有成本效益，低功耗，双向，高速数据传输机制。 版权所有（C）2013，JPO＆INPIT

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