公开(公告)号：JP2008108962A

公开(公告)日：2008-05-08

申请号：JP2006291291

申请日：2006-10-26

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： AKIYAMA MIWAKO ,  NAKAGAWA AKIO ,  KAWAGUCHI YUSUKE ,  ONO SHOTARO ,  YAMAGUCHI YOSHIHIRO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766

Abstract: PROBLEM TO BE SOLVED: To maintain the good tradeoff property of on-resistance and breakdown voltage which are the advantage of MOS transistors of floating construction, at the same time, to improve also turn-on property and switching loss in the time of turn-on of an element.
SOLUTION: In an epitaxial layer 12, a p-type embedded layer 13 A of the bottom is embeddedly formed and further a p-type connection layer 13B which connects the p-type embedded layer 13 and a p-type base layer 14 is embeddedly formed. The impurity concentration of the p-type connection layer 13B is smaller than that of the p-type embedded layer 13A. The p-type base layer 14 is formed by epitaxial growth on the upper surface of the epitaxial layer 12. In a trench T1, a gate electrode 16 composed of polysilicon etc. is embedded through a gate insulating film 15. The depth Dd (p-type embedded layer depth) of the p-type embedded layer 13A from the bottom of the p-type base layer 14 is larger than the distance (protruding distance) Dgp between the bottom face of the gate electrode 16 and the base layer 14.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了保持作为浮动结构的MOS晶体管的优点的导通电阻和击穿电压的良好权衡特性，同时，在时间上改善开启特性和开关损耗 元素的开启。 解决方案：在外延层12中，底部的p型嵌入层13A被嵌入地形成，并且还有一个连接p型嵌入层13和p型基极层的p型连接层13B 14嵌入地形成。 p型连接层13B的杂质浓度比p型嵌入层13A的杂质浓度小。 p型基极层14通过外延生长在外延层12的上表面上形成。在沟槽T1中，由多晶硅等构成的栅电极16通过栅极绝缘膜15嵌入。深度Dd（p p型嵌入层13A的厚度比p型基底层14的底部的距离（突出距离）Dgp大，与栅极电极16的底面和底层14之间的距离（突出距离）Dgp大。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008066708A

公开(公告)日：2008-03-21

申请号：JP2007165879

申请日：2007-06-25

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KAWAGUCHI YUSUKE ,  YAMAGUCHI YOSHIHIRO ,  ONO SHOTARO ,  NAKAGAWA AKIO ,  AKIYAMA MIWAKO ,  NAKAYAMA KAZUYA ,  YAMAGUCHI SHOICHI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7828

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces the channel resistance of a MOSFET to reduce the on-resistance of an element.
SOLUTION: The semiconductor device includes a first conductive drain layer 11, an epitaxial layer 12 formed on the drain layer 11, and a second conductive base layer 13 formed on the surface of the epitaxial layer 12. A plurality of gate electrodes 15 are formed via gate insulating layers 14 so that the base layer 13 is located between the gate electrodes 15. The width x of the base layer 13 located between the gate electrodes 15 is designated to be 0.3 μm or smaller.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种降低MOSFET的沟道电阻以减小元件的导通电阻的半导体器件。 解决方案：半导体器件包括第一导电漏极层11，形成在漏极层11上的外延层12和形成在外延层12的表面上的第二导电基极层13.多个栅电极15 通过栅极绝缘层14形成，使得基极层13位于栅电极15之间。位于栅电极15之间的基极层13的宽度x被指定为0.3μm以下。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007103971A

公开(公告)日：2007-04-19

申请号：JP2007001608

申请日：2007-01-09

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： MATSUDAI TOMOKO ,  HATTORI HIDETAKA ,  NAKAGAWA AKIO

IPC: H01L29/739 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To mount a power device and a control device in one chip together.
SOLUTION: A semiconductor device includes a vertical type device and a control circuit which are formed in an identical substrate. The vertical type device is constituted by a first base layer 13 of a first conductive type which has a first and a second surface regions; a collector layer 10 of a second conductive type which is arranged in the first surface region, and is set to be 1 μm or less in its thickness; a buffer layer 12 of the first conductive type which is arranged between the first base layer 13 and the collector layer 10; a second base layer 14 of the second conductive type which is arranged in the second surface region; an emitter layer 15 of the first conductive type which is arranged in the second base layer 14; a gate insulating film 19A which is arranged on a surface of the second base layer 14 positioned between the emitter layer 15 and the first base layer 13; and a gate electrode 20 which is arranged on the gate insulating film 19A.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：将功率器件和控制器件安装在一个芯片中。 解决方案：半导体器件包括形成在同一衬底中的垂直型器件和控制电路。 垂直型装置由具有第一和第二表面区域的第一导电类型的第一基底层13构成; 布置在第一表面区域中的第二导电类型的集电极层10，其厚度设定为1μm以下。 布置在第一基底层13和收集层10之间的第一导电类型的缓冲层12; 布置在第二表面区域中的第二导电类型的第二基底层14; 布置在第二基层14中的第一导电类型的发射极层15; 布置在位于发射极层15和第一基极层13之间的第二基极层14的表面上的栅极绝缘膜19A; 以及设置在栅极绝缘膜19A上的栅电极20。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007012977A

公开(公告)日：2007-01-18

申请号：JP2005193597

申请日：2005-07-01

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NAKAGAWA AKIO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/739

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727

Abstract: PROBLEM TO BE SOLVED: To provide a method for further fining a semiconductor that has SJ structure. SOLUTION: The semiconductor device comprises a first-conductive first semiconductor layer 11; a first main electrode 22 formed on one side of the first semiconductor layer 11; a first-conductive second semiconductor layer 12, and a second-conductive third semiconductor layer 13, with both the layers 12, 13 being disposed alternately in the surface direction on the other side of the first semiconductor layer 11; a second-conductive fourth semiconductor layer 14 formed on the surfaces of the second and third semiconductor layers 12, 13; a first-conductive fifth semiconductor layer 15 formed on the surface of the fourth semiconductor layer 14; control electrodes formed in trenches via an insulation film, piercing the fourth and fifth semiconductor layers 14, 15 down to the second semiconductor layer 12; a first-conductive sixth semiconductor layer 19 formed after forming the trenches so as to wrap the bottoms of the trenches; and a second main electrode 21 connected to the fourth and fifth semiconductor layers. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种进一步精细化具有SJ结构的半导体的方法。 解决方案：半导体器件包括第一导电第一半导体层11; 形成在第一半导体层11的一侧的第一主电极22; 第一导电第二半导体层12和第二导电第三半导体层13，其中两个层12,13在第一半导体层11的另一侧上在表面方向交替布置; 形成在第二和第三半导体层12,13的表面上的第二导电的第四半导体层14; 形成在第四半导体层14的表面上的第一导电的第五半导体层15; 通过绝缘膜形成在沟槽中的控制电极，将第四和第五半导体层14,15穿过第二半导体层12; 在形成沟槽以便包裹沟槽的底部之后形成的第一导电的第六半导体层19; 以及连接到第四和第五半导体层的第二主电极21。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006012967A

公开(公告)日：2006-01-12

申请号：JP2004184940

申请日：2004-06-23

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ONO SHOTARO ,  KAWAGUCHI YUSUKE ,  NAKAGAWA AKIO

IPC: H01L27/04 ,  H01L21/336 ,  H01L29/06 ,  H01L29/47 ,  H01L29/76 ,  H01L29/78 ,  H01L29/872 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/0696 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that can reduce on-resistance and suppress leak current.
SOLUTION: The semiconductor device is provided with a plurality of trenches 1 that are arranged nearly parallel to each other at a specified interval, a plurality of sources 3 that are formed within the trenches 1 with an insulating layer 2 in between, a source metallic layer 4 formed above the trench 1, an n
- semiconductor area 5 formed between the adjoining trenches 1, an n-type drift layer 6 formed under the trench 1, an n
+ substrate 7 formed under the n-type drift layer 6, and a drain metallic layer 8 formed on the bottom surface of the n
+ substrate 7. The source 3 within the trench 1 is made of p-type polysilicon. The source 3 is in contact with the source metallic layer 4. The n
- semiconductor area 5 and the source metallic layer 4 are Schottky-joined with each other.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供可以降低导通电阻并抑制漏电流的半导体器件。 解决方案：半导体器件设置有以规定的间隔彼此平行布置的多个沟槽1，形成在沟槽1内的多个源3，其间具有绝缘层2， 形成在沟槽1上方的源极金属层4，形成在相邻的沟槽1之间的n - / SP>半导体区域5，形成在沟槽1下面的n型漂移层6， / SP>衬底7，以及形成在n + 衬底7的底表面上的漏极金属层8.沟槽1内的源极3由 p型多晶硅。 源极3与源极金属层4接触。半导体区域5和源极金属层4彼此肖特基接合。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005203766A

公开(公告)日：2005-07-28

申请号：JP2004366329

申请日：2004-12-17

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NAKAMURA KAZUTOSHI ,  YASUHARA NORIO ,  MATSUSHIRO TOMOKO ,  MATSUSHITA KENICHI ,  NAKAGAWA AKIO

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M3/155

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of elevating conversion efficiency by reducing a parasitic inductance and resistance of a DC-DC converter.
SOLUTION: The semiconductor device has a high side switching element 12, a driver circuit 11, and a low side switching element. The high side switching element 12 is formed on a first semiconductor substrate 21, and an input voltage is supplied to one end of its current passage and another end of the current passage is connected to an inductance. The driver circuit 11 is formed on the semiconductor substrate 21 on which the high side switching element 12 is formed and drives the high side switching element 12. The low side switching element is formed on a second semiconductor substrate other than the first semiconductor substrate 21, the inductance is connected to its drain, and a reference potential is supplied to its source.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供能够通过降低DC-DC转换器的寄生电感和电阻来提高转换效率的半导体器件。 解决方案：半导体器件具有高侧开关元件12，驱动电路11和低侧开关元件。 高侧开关元件12形成在第一半导体基板21上，并且输入电压被提供给其电流通路的一端，并且电流通路的另一端连接到电感。 驱动电路11形成在形成有高侧开关元件12的半导体基板21上并驱动高侧开关元件12.低侧开关元件形成在第一半导体基板21以外的第二半导体基板上， 电感连接到其漏极，并将参考电位提供给其源极。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005056912A

公开(公告)日：2005-03-03

申请号：JP2003205983

申请日：2003-08-05

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ONO SHOTARO ,  KAWAGUCHI YUSUKE ,  NAKAGAWA AKIO

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/267 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/42368 ,  H01L29/4933

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of enhancing switching characteristics, and to provide its fabricating process.
SOLUTION: A vertical MOSFET has a base region 22 formed on a drain region 21, and a source region 23 formed in the base region. A trench 24 penetrates the source region from the surface thereof to reach at least the vicinity of the drain region. A gate insulation film 25 is formed on the sidewall and the bottom of the trench and at least a part of a gate electrode 26 is formed in the trench. Impurity concentration profile in the base region has a first peak in the vicinity of the interface between the source region and the base region, and a second peak lower than the first peak in the vicinity of the interface between the base region and the drain region. The first peak determines a threshold voltage, and the second peak determines the dosage of the base region.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够提高开关特性并提供其制造工艺的半导体器件。 解决方案：垂直MOSFET具有形成在漏区21上的基极区22和形成在基极区中的源极区23。 沟槽24从其表面穿透源极区域至少到达漏极区域附近。 在沟槽的侧壁和底部上形成栅极绝缘膜25，并且在沟槽中形成栅电极26的至少一部分。 基极区域中的杂质浓度分布在源区域和基极区域之间的界面附近具有第一峰值，并且比基极区域和漏极区域之间的界面附近的第一峰值低的第二峰值。 第一峰值确定阈值电压，第二峰值确定基本区域的剂量。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004327598A

公开(公告)日：2004-11-18

申请号：JP2003118462

申请日：2003-04-23

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ONO SHOTARO ,  KAWAGUCHI YUSUKE ,  NAKAGAWA AKIO

IPC: H01L29/78 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76

CPC classification number: H01L29/41741 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7813

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device whose on-state resistance is low and which has high-speed switching characteristic. SOLUTION: The semiconductor device is constituted of an n - -type epitaxial layer 12; a p-type base region 13 formed on the n - -type epitaxial layer 12; an n + -type source region 14 formed on the p-type base region 13; a trench 15 which is formed from a surface of the n + -type source region 14 over the n + -type source region 14 and the p-type base region 13, and penetrates the n + -type source region 14 whose depth is shallower than the deepest bottom of the p-type base region 13, and in which the p-type base region 13 does not exist under the bottom surface; gate electrodes 18 which are arranged on both facing side surfaces of the trench 15 through a gate insulating film 17 and isolated from each other; and conductive material which is formed between the gate electrodes 18 on both of the side surfaces of the trench 15 through an insulating film 19. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种导通电阻低且具有高速开关特性的半导体器件。 解决方案：半导体器件由n型SP型 - 外延层12构成; 形成在n型SP型 - 外延层12上的p型基极区域13; 形成在p型基极区域13上的n

公开(公告)号：JP2004193630A

公开(公告)日：2004-07-08

申请号：JP2004064661

申请日：2004-03-08

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： MATSUSHIRO TOMOKO ,  YASUHARA NORIO ,  NAKAGAWA AKIO ,  YAMAGUCHI YOSHIHIRO ,  OMURA ICHIRO ,  FUNAKI HIDEYUKI

IPC: H01L29/74 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/786 ,  H01L29/861

CPC classification number: H01L29/407

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric isolation structured high withstand voltage semiconductor element capable of obtaining a sufficient high withstand voltage characteristic by a thin active layer. SOLUTION: The semiconductor element is provided with a semiconductor substrate and the active layer having a thickness of 0.3 μm or less comprising a high resistance semiconductor which is formed on the semiconductor substrate via an insulator film. For the active layer, impurity concentration distribution in a lateral direction forms steps varying from 2 to 10 steps. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004140235A

公开(公告)日：2004-05-13

申请号：JP2002304631

申请日：2002-10-18

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KAWAGUCHI YUSUKE ,  SUESHIRO TOMOKO ,  NAKAMURA KAZUTOSHI ,  NAKAGAWA AKIO

IPC: H01L21/331 ,  H01L29/73

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which never breaks even when applied with a high voltage as compared with a junction separation type device, as a dielectric separation type semiconductor device which uses an SOI substrate.
SOLUTION: Apart from an n-type collector layer 24, a p
- -type impurity area 31 is formed which has lower impurity density than a p-type base layer 21 while connected to the p-type base layer 21. Consequently, congestion of an electric field which is nearby the border between an n-type active layer 12 and the p-type base layer 21 and in a high-electric-field area facing the n-type collector layer 24 is reduced to enable application of a higher voltage than usual.
COPYRIGHT: (C)2004,JPO