公开(公告)号：JP2009158643A

公开(公告)日：2009-07-16

申请号：JP2007333671

申请日：2007-12-26

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： UCHIJO TATSUO ,  OMURA ICHIRO

IPC: H01L29/861 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having high performance particularly with respect to a structure of a transverse PiN diode and a method of manufacturing the same. SOLUTION: In this semiconductor device, in an SOI substrate 4 comprising a semiconductor substrate 1, a silicon oxide film 2 formed on the semiconductor substrate 1 and a first conductive-type semiconductor layer 3 formed on the silicon oxide film 2, a first diffusion layer 5 and a second diffusion layer 6 distant from each other are provided. The first diffusion layer 5 is a second conductive-type diffusion layer doped more heavily than that of the semiconductor layer 3 and the second diffusion layer 6 is a first conductive-type diffusion layer doped more heavily than that of the semiconductor layer 3. On the SOI substrate 4, first field plates 9A, 10A, 11A are formed by a wiring layer electrically connected with a first electrode 9A of the first diffusion layer 5, and second field plates 9B, 10B, 11B are formed by a wiring layer electrically connected with a second electrode 9B of the second diffusion layer 6. The first field plates 9A, 10A, 11A and the second field plates 9B, 10B, 11B are insulated from each other by insulating films 8, 12. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有高性能的半导体器件，特别是关于横向PiN二极管的结构及其制造方法。 解决方案：在该半导体器件中，在包括半导体衬底1的SOI衬底4中，形成在半导体衬底1上的氧化硅膜2和形成在氧化硅膜2上的第一导电型半导体层3， 提供第一扩散层5和彼此远离的第二扩散层6。 第一扩散层5是比半导体层3更加掺杂的第二导电型扩散层，第二扩散层6是比半导体层3掺杂更多的第一导电型扩散层。在 SOI基板4，第一场板9A，10A，11A由与第一扩散层5的第一电极9A电连接的布线层形成，第二场板9B，10B，11B由与 第二扩散层6的第二电极9B。第一场板9A，10A，11A和第二场板9B，10B，11B通过绝缘膜8,12彼此绝缘。版权所有（C） 2009年，JPO＆INPIT

公开(公告)号：JP2008277597A

公开(公告)日：2008-11-13

申请号：JP2007120485

申请日：2007-05-01

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUDA MASANORI ,  MATSUSHITA KENICHI ,  OMURA ICHIRO

IPC: H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve both forward and reverse breakdown voltage characteristics in a high breakdown voltage semiconductor device.
SOLUTION: On one surface of a first conductivity type first base layer having a first impurity concentration, a first conductivity type buffer layer having a second impurity concentration higher than the first impurity concentration is formed. On the other surface of the first base layer, a second conductivity type second base layer is formed. Also, on the side opposite to the first base layer of the buffer layer, a second conductivity type collector layer is formed. The buffer layer is formed so as to have a first thickness in a center region and have a second thickness less than the first thickness in a peripheral region surrounding the center region. The second base layer is formed in the center region.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提高高击穿电压半导体器件中的正向和反向击穿电压特性。 解决方案：在具有第一杂质浓度的第一导电型第一基底层的一个表面上，形成具有高于第一杂质浓度的第二杂质浓度的第一导电型缓冲层。 在第一基底层的另一个表面上，形成第二导电类型的第二基底层。 此外，在与缓冲层的第一基底层相对的一侧上形成第二导电型集电体层。 缓冲层形成为在中心区域具有第一厚度并且在围绕中心区域的周边区域中具有小于第一厚度的第二厚度。 第二基层形成在中心区域。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006340390A

公开(公告)日：2006-12-14

申请号：JP2006203525

申请日：2006-07-26

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： OMURA ICHIRO ,  DOMON TOMOKAZU ,  SAITO SUZUO ,  OHASHI HIROMICHI ,  SUGIYAMA KOICHI ,  EICHER SIMON ,  OGURA TSUNEO

IPC: H03K17/08 ,  H01L29/739 ,  H01L29/78 ,  H03K17/56

CPC classification number: H01L2224/0603 ,  H01L2224/34 ,  H01L2224/37147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4846 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/37599 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To improve reliability of semiconductor devices by enhancing stability of current density to prevent current concentration, oscillation and the like. SOLUTION: The driving device for semiconductor devices improves reliability of the semiconductor devices in the following way. In turning off mutually parallel-connected insulated-gate bipolar semiconductor devices, voltage of each control electrode is reduced down to threshold voltage Vth or lower of each bipolar semiconductor devices before the voltage between main electrodes rises 1/5 or higher of the applied voltage Vcc in the off state. By stopping injection of electrons before the rise of the voltage between main electrodes, stability of the current density is enhanced, preventing current concentration, oscillation and the like. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过提高电流密度的稳定性来提高半导体器件的可靠性，以防止电流集中，振荡等。 解决方案：半导体器件的驱动装置以下列方式提高半导体器件的可靠性。 在关闭互相并联连接的绝缘栅双极半导体器件时，在主电极之间的电压升高到施加电压Vcc的1/5以上之前，每个控制电极的电压降低到每个双极性半导体器件的阈值电压Vth或更低 处于关闭状态。 通过在主电极之间的电压升高之前停止电子注入，电流密度的稳定性提高，防止电流集中，振荡等。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006314112A

公开(公告)日：2006-11-16

申请号：JP2006141951

申请日：2006-05-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： OMURA ICHIRO ,  WOLFGANG FIKTONNER ,  NINOMIYA HIDEAKI ,  OHASHI HIROMICHI ,  OGURA TSUNEO

IPC: H03K17/08 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/739 ,  H01L29/78 ,  H02M1/08 ,  H03K17/56

Abstract: PROBLEM TO BE SOLVED: To enhance reliability by stabilizing gate voltage, even at high voltage, high current, preventing current nonuniformity and oscillation, and the like, thereby protecting the device against breakdowns. SOLUTION: In the method for controlling the semiconductor device, having two main electrodes and a control electrode part which controls current between the main electrodes, in a detection process, an amount of charge accumulated at the control electrode part is detected, based on voltage of the control electrode part. In a control process, voltage applied to the control electrode part and/or current flow to the control electrode part is controlled, based on the amount of charge detected by the detecting process. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了通过稳定栅极电压来提高可靠性，即使在高电压，高电流下，防止电流不均匀和振荡等，从而保护器件免于故障。 解决方案：在用于控制半导体器件的方法中，具有两个主电极和控制电极部分，其控制主电极之间的电流，在检测过程中，基于控制电极部分累积的电荷量被检测 控制电极部分的导通电压。 在控制过程中，基于由检测处理检测到的电荷量，控制施加到控制电极部分的电压和/或流向控制电极部分的电流。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006202837A

公开(公告)日：2006-08-03

申请号：JP2005010480

申请日：2005-01-18

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAITO WATARU ,  OMURA ICHIRO

IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device for an electric power in which an element breakdown voltage is sufficiently high and an on-state resistance is sufficiently low.
SOLUTION: A power MOSFET includes a drain electrode 1 formed along a substrate surface, an n
+ drain layer 2 formed on the drain electrode 1, a drift layer 3 of super junction structure formed on the n
+ drain layer 2, a p base layer 4 selectively formed in the part on the drift layer 3, an n
+ source layer 5 formed selectively on the p base layer 4, a source electrode 6 formed on the p base layer 4 and the n
+ source layer 5, a drift layer 3, a source electrode 6 formed on the p base layer 4 and the n
+ source layer 5, a drift layer 3, a gate electrode 8 arranged adjacently to the p base layer 4 and the n
+ source layer 5 through a gate insulating film 7, and a depletion layer shielding part 9 formed in the end of the drift layer 3 to prevent the widening of the depletion layer. When the drift layer 3 is formed, since the substrate flattening is performed so that the p-type epitaxial growth layer 23 may remain on the substrate front surface, the drift layer 3 does not become thin too much, and there is no possibility that the breakdown voltage may become low.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供元件击穿电压足够高并且导通电阻足够低的电力的半导体器件。 解决方案：功率MOSFET包括沿着衬底表面形成的漏电极1，形成在漏电极1上的n + 漏极层2，选择性地形成在漂移层3上的部分中的基极层4，在p基底层4上选择性地形成的n + SP源极层5， 形成在p基极层4和n + SP + +源极层5上的源电极6，漂移层3，形成在p基极层4上的源极6和n + / SP>源极层5，漂移层3，通过栅极绝缘膜7与p基极层4和n + SP源极层5相邻布置的栅电极8和耗尽层屏蔽 部分9形成在漂移层3的末端，以防止耗尽层的扩大。 当形成漂移层3时，由于进行基板平坦化，使得p型外延生长层23可能保留在基板前表面上，所以漂移层3不会变得太薄，并且不可能 击穿电压可能会变低。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006179598A

公开(公告)日：2006-07-06

申请号：JP2004369713

申请日：2004-12-21

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAITO WATARU ,  OMURA ICHIRO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/7397 ,  H01L29/872

Abstract: PROBLEM TO BE SOLVED: To improve withstand voltage without complicating a process in a power semiconductor device having a super junction structure. SOLUTION: The power semiconductor device includes a first conductivity type second semiconductor layer 2, and a second conductivity type third semiconductor layer 3 alternately disposed on a first conductivity type first semiconductor layer 1. It further includes second conductivity type fourth semiconductor layers 4 disposed respectively to make contact with the upper portion of the third semiconductor layer, between the second semiconductor layers and first conductivity type fifth semiconductor layers 5 formed respectively on the surface of the fourth semiconductor layer. The first semiconductor layer 1 is lower than the second semiconductor layer 2 in first conductivity type impurity concentration. The third semiconductor layer 3 includes a fundamental part 3F and a high impurity amount part 3H formed locally such that the amount of the impurity becomes larger than the fundamental part in a depthwise direction. The amount of the impurity is restricted by the total amount of the second conductivity type impurity in a lateral cross section. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提高耐压而不使具有超结结构的功率半导体器件中的工艺复杂化。 解决方案：功率半导体器件包括交替地布置在第一导电型第一半导体层1上的第一导电类型的第二半导体层2和第二导电类型的第三半导体层3，还包括第二导电类型的第四半导体层4 分别设置在与第四半导体层的表面分别形成的第二半导体层和第一导电型第五半导体层5之间与第三半导体层的上部接触。 第一半导体层1的第一导电型杂质浓度低于第二半导体层2。 第三半导体层3包括基本部分3F和高杂质量部分3H，其局部地形成使得杂质的量在深度方向上大于基本部分。 杂质的量受横向截面中​​第二导电类型杂质的总量的限制。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006108659A

公开(公告)日：2006-04-20

申请号：JP2005264148

申请日：2005-09-12

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NUMATA HIDEO ,  EZAWA HIROKAZU ,  TAKUBO TOMOAKI ,  TAKAHASHI KENJI ,  AOKI HIDEO ,  HARADA SUSUMU ,  KANEKO HISAFUMI ,  IKEGAMI HIROSHI ,  MATSUO MIE ,  OMURA ICHIRO

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L2224/16

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the device, in which the production process can be simplified and the production cost can be reduced, as compared to prior art.
SOLUTION: A one-side copper-foil resin sheet is made contact with and laminated on each of both front and back surfaces of the semiconductor substrate 1 provided with through holes 4, with a resin surface of the sheet kept in contact with each of both surfaces of the substrate 1, and the inner surface of the through hole 4 and both surfaces of the semiconductor substrate 1 are covered with an insulating resin layer 5, formed by laminating one-side copper-foil resin sheets. Outside the insulating resin layer 5, in addition, there are formed wiring layers 6, each having a double-layer structure made up of a copper foil pattern layer and a copper plated layer formed thereon. Furthermore, a post 7 made of electrically conductive material, such as copper, is formed on the insulating resin layer 5 in the inside of the through hole 4 so as to electrically connect the wiring layers on both surfaces of the semiconductor substrate 1.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：与现有技术相比，提供一种半导体器件和制造该器件的方法，其中可以简化制造工艺并且可以降低生产成本。 解决方案：将单面铜箔树脂片与设置有通孔4的半导体基板1的前表面和后表面接触并层压，片材的树脂表面保持与 基板1的两面以及贯通孔4的内表面和半导体基板1的两面都被绝缘树脂层5覆盖，所述绝缘树脂层5通过层叠一面的铜箔树脂片而形成。 另外，在绝缘性树脂层5的外侧形成有由铜箔图案层和形成在其上的镀铜层构成的双层结构的布线层6。 此外，在通孔4的内部的绝缘树脂层5上形成由诸如铜的导电材料制成的柱7，以便电连接半导体衬底1的两个表面上的布线层。

版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006086354A

公开(公告)日：2006-03-30

申请号：JP2004269955

申请日：2004-09-16

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAITO WATARU ,  OMURA ICHIRO

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/06 ,  H01L29/417 ,  H01L29/47 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L29/7787 ,  H01L29/2003

Abstract: PROBLEM TO BE SOLVED: To provide the nitride system semiconductor device of a high breakdown strength and a low ON resistance. SOLUTION: The nitride system semiconductor device has a first semiconductor layer 1 substantially composed of a nitride system semiconductor, and a second semiconductor layer 2 substantially composed of the nitride system semiconductor of a non-dope or first conductive type arranged on the first semiconductor layer. The first and second semiconductor layers form a hetero interface. A gate electrode 11 is arranged on the second semiconductor layer. First and second trenches 3, 4 are formed on the surface of the second semiconductor layer so as to sandwich the gate electrode therebetween. A first conductive type of third and fourth semiconductor layers 5, 6 substantially composed of the diffused layer of a lower resistance than the first and second semiconductor layers are formed on the surface of the first and second trenches. The third and fourth semiconductor layers 5, 6 are electrically connected to a source electrode 15 and a drain electrode 16. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有高击穿强度和低导通电阻的氮化物系半导体器件。 解决方案：氮化物系半导体器件具有基本上由氮化物系半导体构成的第一半导体层1和基本上由布置在第一层上的非掺杂或第一导电类型的氮化物系半导体构成的第二半导体层2 半导体层。 第一和第二半导体层形成异质界面。 栅电极11布置在第二半导体层上。 第一和第二沟槽3,4形成在第二半导体层的表面上，以便将栅电极夹在其间。 在第一和第二沟槽的表面上形成有基本上由比第一和第二半导体层低的电阻的扩散层组成的第一和第四半导体层5,6的第一导电类型。 第三和第四半导体层5,6与源电极15和漏电极16电连接。版权所有：（C）2006，JPO＆NCIPI

公开(公告)号：JP2006054954A

公开(公告)日：2006-02-23

申请号：JP2004234085

申请日：2004-08-11

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： OMURA ICHIRO

IPC: H02M1/08

CPC classification number: H03K17/04123 ,  H03K17/6877

Abstract: PROBLEM TO BE SOLVED: To provide a circuit and a method for driving a gate of a power MOSFET wherein gate driving loss is reduced with an increase in frequency, a gate current can be varied to a desired value, and malfunctions can be prevented.
SOLUTION: Bridges are constructed of switches SW1 to SW4 and diodes SBD1 to SBD4. An inductance element L1 for storage of energy is connected between the junction point between the switches SW1 and SW2 and the junction point between the switches SW3 and SW4. The switches SW1 to SW4 are controlled by a switching control circuit SWC for driving a MOSFET M1. When the MOSFET M1 is turned on, driving loss is reduced by taking the following procedure: with the switch SW4 kept on, the switch SW1 is turned on to pass a current through the inductance element L1 to store energy there. When the current reaches a predetermined value, the switch SW4 is turned off and the gate voltage of the MOSFET M1 is increased with the stored energy. The switch SW3 is turned on, and then the switch SW1 is turned off to regenerate energy.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供用于驱动功率MOSFET的栅极的电路和方法，其中栅极驱动损耗随着频率的增加而减小，栅极电流可以变化到期望值，并且故障可以是 预防。 解决方案：桥由开关SW1至SW4和二极管SBD1至SBD4构成。 用于存储能量的电感元件L1连接在开关SW1和SW2之间的连接点与开关SW3和SW4之间的连接点之间。 开关SW1至SW4由用于驱动MOSFET M1的开关控制电路SWC控制。 当MOSFET M1导通时，通过以下步骤来降低驱动损耗：开关SW4保持导通，开关SW1导通，使电流通过电感元件L1，在那里存储能量。 当电流达到预定值时，开关SW4断开，MOSFET M1的栅极电压随存储能量增加。 开关SW3导通，然后断开开关SW1以再生能量。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006005005A

公开(公告)日：2006-01-05

申请号：JP2004177151

申请日：2004-06-15

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAITO WATARU ,  OMURA ICHIRO

IPC: H01L21/338 ,  H01L21/28 ,  H01L21/76 ,  H01L27/06 ,  H01L27/095 ,  H01L29/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/41 ,  H01L29/417 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/109

CPC classification number: H01L29/404 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a nitrogen-compound-containing semiconductor device which is provided with heterostructure that is formed on a silicon substrate and includes a nitrogen-compound-containing semiconductor layer, and which has high breakdown voltage of several hundreds V or more. SOLUTION: The nitrogen-compound-containing semiconductor device is provided with a silicon substrate, a first aluminum nitride gallium (Al x Ga 1-x N(0≤x≤1)) layer that is formed like an island as a channel layer on the silicon substrate, and second aluminum nitride gallium (Al y Ga 1-y N(0≤y≤1, x COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种含氮化合物的半导体器件，其具有形成在硅衬底上并且包含含氮化合物的半导体层的异质结构，并且具有几百个高的击穿电压 V以上。 解决方案：含氮化合物的半导体器件设置有硅衬底，第一氮化铝镓（Al x Ga 1-x N（0≤ x≤1））层，作为硅衬底上的沟道层形成为岛状，并且第二氮化铝镓（Al 3 S） 在第一氮化铝镓层上形成作为第一导电型或i型阻挡层的层）。 版权所有（C）2006，JPO＆NCIPI