公开(公告)号：JP2011044717A

公开(公告)日：2011-03-03

申请号：JP2010185362

申请日：2010-08-20

Applicant: Icemos Technology Ltd ,  アイスモス・テクノロジー・リミテッドIcemos Technology Ltd

Inventor： WILSON ROBIN ,  MACNAMARA CORMAC

IPC: H01L31/09

CPC classification number: H01L31/1804 ,  H01L23/481 ,  H01L27/1446 ,  H01L27/14663 ,  H01L31/105 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/131 ,  Y02E10/547 ,  H01L2924/014

Abstract: PROBLEM TO BE SOLVED: To provide a photodetector array that overcomes restriction on a conventional photodetector array so as to have improved performance.
SOLUTION: The photodetector array includes a plurality of photodetectors formed by a high-resistivity/low-doping-concentration first semiconductor substrate and a low-resistivity/high-doping-concentration second semiconductor substrate. The first/second semiconductor substrates are directly bonded to each other by a silicon-to-silicon atomic bond at a bond interface, thereby configuring a sharp transition from the first substrate to the second substrate. A method of manufacturing the photodetector array is also configured.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供克服对常规光电检测器阵列的限制以便具有改进的性能的光电检测器阵列。 解决方案：光电检测器阵列包括由高电阻率/低掺杂浓度的第一半导体衬底和低电阻率/高掺杂浓度的第二半导体衬底形成的多个光电检测器。 第一/第二半导体衬底通过在接合界面处的硅 - 硅原子键彼此直接接合，从而构成从第一衬底到第二衬底的尖锐过渡。 还构造了一种制造光电检测器阵列的方法。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2009040654A1

公开(公告)日：2009-04-02

申请号：PCT/IB2008/002528

申请日：2008-09-26

Applicant: ICEMOS TECHNOLOGY LTD ,  ISHIGURO, Takeshi ,  GRIFFIN, Hugh J. ,  SUGIURA, Kenji

Inventor： ISHIGURO, Takeshi ,  GRIFFIN, Hugh J. ,  SUGIURA, Kenji

IPC: H01L29/06

CPC classification number: H01L29/0634

Abstract: A method of manufacturing a "super junction device includes providing a semiconductor wafer having a plurality of dies (320a, 321a). A first plurality of trenches (323a) having a first orientation are formed in a first die (320a). A second plurality of trenches having a second orientation are formed in a second die (321a). The second orientation is different from the first orientation.

Abstract translation: 一种制造“超接合器件”的方法包括提供具有多个管芯（320a，321a）的半导体晶片，在第一管芯（320a）中形成具有第一取向的第一多个沟槽（323a），第二多个 具有第二取向的沟槽形成在第二模具（321a）中，第二取向与第一取向不同。

公开(公告)号：WO2009040650A1

公开(公告)日：2009-04-02

申请号：PCT/IB2008/002520

申请日：2008-09-26

Applicant: ICEMOS TECHNOLOGY LTD ,  ISHIGURO, Takeshi ,  GRIFFIN, Hugh, J. ,  SUGIURA, Kenji

Inventor： ISHIGURO, Takeshi ,  GRIFFIN, Hugh, J. ,  SUGIURA, Kenji

IPC: H01L29/06

CPC classification number: H01L29/0634

Abstract: A method of manufacturing a super junction device includes providing a semiconductor wafer having at least one die (220a). At- least one first trench (222a) having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.

Abstract translation: 制造超接合器件的方法包括提供具有至少一个管芯（220a）的半导体晶片。 在至少一个管芯中形成至少一个具有第一取向的第一沟槽（222a）。 在至少一个管芯中形成具有不同于第一取向的第二取向的至少一个第二沟槽。

公开(公告)号：US20220028973A1

公开(公告)日：2022-01-27

申请号：US16934738

申请日：2020-07-21

Applicant: Icemos Technology Ltd.

Inventor： Kiraneswar Muthuseenu ,  Samuel Anderson ,  Takeshi Ishiguro

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm−3 and 1.5×1020 cm−3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.

公开(公告)号：US09147751B2

公开(公告)日：2015-09-29

申请号：US14580730

申请日：2014-12-23

Applicant: Icemos Technology Ltd.

Inventor： Samuel Anderson ,  Takeshi Ishiguro

IPC: H01L29/74 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/73 ,  H01L29/737 ,  H01L29/739 ,  H01L29/861 ,  H01L21/265 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7308 ,  H01L29/7371 ,  H01L29/7393 ,  H01L29/74 ,  H01L29/861

Abstract: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.

Abstract translation: 提供具有端子结构的窄表面布局的超结半导体器件和制造器件的方法。 端子结构的窄表面布局部分地通过在源体接触界面处将源电极连接到半导体衬底内的体接触区域而实现，所述体接触界面包括至少第一侧的身体接触区域，而不是第一 半导体衬底的主表面。

公开(公告)号：US20110193176A1

公开(公告)日：2011-08-11

申请号：US13091410

申请日：2011-04-21

Applicant: Samuel Anderson ,  Koon Chong So

Inventor： Samuel Anderson ,  Koon Chong So

IPC: H01L27/06 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/872

Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.

Abstract translation: 半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。 更具体地说，超结半导体器件包括无衬里和密封的沟槽。 沟槽具有由半导体材料形成的侧壁。 沟槽用密封材料密封，使得沟槽是气密的。 第一和第二区域被沟槽分开。 第一区域可以包括超连接肖特基二极管或MOSFET。 在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

公开(公告)号：US20110068440A1

公开(公告)日：2011-03-24

申请号：US12914623

申请日：2010-10-28

Applicant: Takeshi Ishiguro ,  Hugh J. Griffin ,  Kenji Sugiura

Inventor： Takeshi Ishiguro ,  Hugh J. Griffin ,  Kenji Sugiura

IPC: H01L21/265 ,  H01L29/06

CPC classification number: H01L21/26586 ,  H01L29/045 ,  H01L29/0634

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.

Abstract translation: 一种制造半导体器件的方法包括提供半导体晶片并且在晶片中形成具有第一和第二侧壁的晶片中的至少一个第一沟槽和在晶片上的第一取向。 所述至少一个第一沟槽的第一侧壁在第一注入方向上注入具有第一导电性的掺杂剂。 至少一个第一沟槽的第一侧壁在第二植入方向上注入第一导电性的掺杂剂。 第二注入方向与第一注入方向正交。 第一和第二注入方向与第一侧壁不正交。

公开(公告)号：US07910479B2

公开(公告)日：2011-03-22

申请号：US12411933

申请日：2009-03-26

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/44

CPC classification number: H01L27/1446 ,  H01L21/76898 ,  H01L31/18

Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.

Abstract translation: 一种制造光电二极管阵列的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 半导体衬底具有靠近第一主表面的第一导电的第一层和靠近第二主表面的第二导电的第二层。 在衬底中形成通孔，该通孔相对于第一主表面延伸到第一深度位置。 通孔具有第一宽高比。 通常在形成通孔的同时，在与通孔间隔开的基板中形成隔离沟槽，其相对于第一主表面延伸到第二深度位置。 隔离沟槽具有与第一宽高比不同的第二宽高比。

公开(公告)号：US20110042576A1

公开(公告)日：2011-02-24

申请号：US12860024

申请日：2010-08-20

Applicant: Robin WILSON ,  Cormac MACNAMARA

Inventor： Robin WILSON ,  Cormac MACNAMARA

IPC: G01T1/20 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/1804 ,  H01L23/481 ,  H01L27/1446 ,  H01L27/14663 ,  H01L31/105 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/131 ,  Y02E10/547 ,  H01L2924/014

Abstract: A photodetector array comprises a plurality of photodetectors formed by a high resistivity low doping concentration first semiconductor substrate and a low resistivity high doping concentration second semiconductor substrate. The first and second semiconductor substrates are directly bonded together with a silicon-to-silicon atomic bond at a bond interface, thereby providing a sharp transition from the first substrate to the second substrate. A method of making the photodetector array is also provided.

Abstract translation: 光电检测器阵列包括由高电阻率低掺杂浓度第一半导体衬底和低电阻率高掺杂浓度第二半导体衬底形成的多个光电检测器。 第一和第二半导体衬底在键合界面处以硅 - 硅原子键直接结合在一起，从而提供从第一衬底到第二衬底的尖锐过渡。 还提供了制造光电检测器阵列的方法。

公开(公告)号：US20090253261A1

公开(公告)日：2009-10-08

申请号：US12485096

申请日：2009-06-16

Applicant: Cormac MACNAMARA ,  Hugh J. GRIFFIN ,  Robin WILSON

Inventor： Cormac MACNAMARA ,  Hugh J. GRIFFIN ,  Robin WILSON

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  B81B2207/096 ,  B81C1/00301 ,  H01L23/481 ,  H01L2224/13099 ,  H01L2924/09701 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other, forming in the semiconductor substrate at least one trench of a predetermined geometric shape in the first main surface, lining the at least one trench with a dielectric material, filling the at least one trench with a conductive material, electrically connecting an electrical component to the conductive material of the at least one trench at the first main surface; and mounting a cap to the first main surface. The at least one trench extends to a first depth position D in the semiconductor substrate. The cap encloses at least a portion of the electrical component and the electrical connection between the electrical component and the conductive material.

Abstract translation: 一种制造半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底，在所述半导体衬底中形成在所述第一主表面中具有预定几何形状的至少一个沟槽， 电介质材料，用导电材料填充所述至少一个沟槽，在第一主表面处将电气部件电连接到所述至少一个沟槽的导电材料; 并将帽安装到第一主表面上。 至少一个沟槽延伸到半导体衬底中的第一深度位置D。 盖子包围电气部件的至少一部分以及电气部件和导电材料之间的电连接。