公开(公告)号：JP2017084434A

公开(公告)日：2017-05-18

申请号：JP2016102448

申请日：2016-05-23

Applicant: 力成科技股▲分▼有限公司 ,  Powertech Technology Inc

Inventor： YEH CHIH-HUI ,  LEE SHII

IPC: G11C29/56 ,  G01R31/28

CPC classification number: H04L43/50 ,  H04B7/0413

Abstract: 【課題】高周波メモリの試験装置及び試験方法を提供する【解決手段】本発明は一種の高周波メモリの試験方法を開示し、先ず、変換インタフェース110、テスタ120と素子結合板130を含む高周波メモリの試験装置100を提供する。テスタ120は変換インタフェース110を介して素子結合板130と電気的に接続し、変換インタフェース110は、テスタ120が出力した第1試験信号と第2試験信号を合併して高調波試験信号を生成し、生成した高調波試験信号を素子結合板130に送信し、そのように、素子結合板130に配置した少なくとも2個の被試験メモリパッケージに対し試験を行なう。【選択図】図3

公开(公告)号：JP2013062470A

公开(公告)日：2013-04-04

申请号：JP2011201621

申请日：2011-09-15

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： CHEN HWI-CHANG

IPC: H01L25/04 ,  H01L23/02 ,  H01L25/18

CPC classification number: H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing substrate cost and improving peeling caused by exposure in the side of a substrate.SOLUTION: A substrate 120 of a semiconductor device 100 that has a packaging structure for a multi-chip memory with a small substrate, is adhered to a lower part of a chip mounting body 110 and has an upper surface 121 and a lower surface 122. The upper surface 121 is exposed to a hollow area 11. A plurality of contact pads 123 are installed on the lower surface 122. A first chip 130 is installed on the substrate 120 and located in the hollow area 111. A second chip 140 is installed on the chip mounting body 110. A sealing body 150 tightly seals the chip mounting body 110, the upper surface 121 of the substrate 120, the first chip 130, and the second chip 140. The outline of the substrate 120 is smaller than that of the sealing body 150, and connected with a plurality of support bars 112 around the chip mounting body 110. A group of the support bars 112 extends to the side of the sealing body 150.

Abstract translation: 要解决的问题：提供能够降低基板成本并改善由于在基板侧暴露而引起的剥离的半导体器件。 解决方案：具有用于具有小基板的多芯片存储器的封装结构的半导体器件100的衬底120粘附到芯片安装体110的下部，并且具有上表面121和下表面 表面122.上表面121暴露于中空区域11.多个接触焊盘123安装在下表面122上。第一芯片130安装在基板120上并且位于中空区域111中。第二芯片 140安装在芯片安装体110上。密封体150紧密地密封芯片安装体110，基板120的上表面121，第一芯片130和第二芯片140.基板120的轮廓较小 并且与芯片安装体110周围的多个支撑杆112连接。一组支撑杆112延伸到密封体150的侧面。（C）2013 ，JPO＆INPIT

公开(公告)号：JP2010160074A

公开(公告)日：2010-07-22

申请号：JP2009002862

申请日：2009-01-08

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： SU TING FENG

IPC: G01N3/303

Abstract: PROBLEM TO BE SOLVED: To provide a drop tester for a semiconductor chip package product and usage thereof.
SOLUTION: The drop tester 100 includes a drop starting angle setting tool 120 placed on a fixed rack 110 horizontally movably to set a DUT (device under test) 10 at a prescribed angle, and secured to a clamp 130 accurately, rapidly, and safely. A tool like this provides a second reference plane 123 to couple it to an elevatable/adjustable test sample table 121. The sample table 121 comprising a first reference plane 122 allows the DUT 10 to be attached to or detached from the tool 120 such that neither friction arises nor the DUT 10 is moved after it is held by the clamp 130. Accordingly, the DUT 10 can be not only accurately positioned but the tool 120 can be returned rapidly and safely to a reference position by using the design of a slide rail and a stopper.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于半导体芯片封装产品的跌落测试仪及其用途。 解决方案：跌落测试器100包括放置在固定架110上的液滴起始角度设定工具120，水平可移动地将DUT（被测设备）10以规定的角度设置，并且精确，准确地固定在夹具130上， 并安全。 这样的工具提供第二参考平面123以将其耦合到可升高/可调节的测试样品台121.包括第一参考平面122的样品台121允许DUT 10附接到工具120或从工具120拆卸，使得两者 产生摩擦，也不会在夹具130保持DUT 10之后移动。因此，DUT 10不仅可以精确定位，而且可以通过使用滑轨的设计将工具120快速安全地返回到参考位置 和塞子。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009231637A

公开(公告)日：2009-10-08

申请号：JP2008076808

申请日：2008-03-24

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： YU BINGXUN ,  HONG JINWEI

IPC: H01L23/12 ,  H01L23/29

CPC classification number: H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor-package structure having a heat-dissipating piece. SOLUTION: The semiconductor-package structure having the heat-dissipating pieces is constituted of a substrate, having a chip-carrier region and surrounding and forming a plurality of bored holes around the chip-carrier region and chips fitted in the chip-carrier region and electrically connected to the substrate. The semiconductor-package structure having the heat-dissipating pieces is, further, constituted of the heat-dissipating pieces suitable for the upper sections of the chips and having a plurality of supporting sections, extending from the upper surface to the lower surface of the substrate through boring, and package gel coating the chips and the partial substrate and the heat-dissipating pieces. Heat-dissipating effect is increased by the support sections for the heat-dissipating pieces, and warpage of package can be reduced. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有散热片的半导体封装结构。 解决方案：具有散热片的半导体封装结构由具有芯片载体区域并围绕芯片载体区域周围并形成多个钻孔的基板和装配在芯片载体区域中的芯片构成， 载体区域并且电连接到衬底。 具有散热片的半导体封装结构还由适用于芯片的上部的散热片构成，并且具有从基板的上表面延伸到下表面的多个支撑部 通过镗孔，并将芯片和部分基板以及散热片进行包胶。 通过用于散热片的支撑部分增加散热效果，并且可以减小包装的翘曲。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009200253A

公开(公告)日：2009-09-03

申请号：JP2008040381

申请日：2008-02-21

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： FAN WEN-JENG ,  HSU YU-MEI

IPC: H01L21/60

CPC classification number: H01L2224/05554 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that packages chips having different sizes and a different bonding pad positions and is suitable for sharing. SOLUTION: The semiconductor device includes the chip 220 having a plurality of first leads 210 of a lead frame having a zigzag type finger 211 including first and second finger sections 212, 213 subjected to bending connection in a V shape mutually and a plurality of the bonding pads 222. One end of bonding wires 231, 232 is connected to a group of bonding pads 222 of the chip 220, and the other end is arbitrarily connected to one of the sets of the first and second finger sections 212, 213. The direction of the wire bonding forms a first angle with respect to the expansion direction of the set to which one of the first and second finger sections 212, 213 is connected, forms a second angle with respect to the expansion direction of the set to which one of the first and second finger sections 212, 213 is not connected, the bonding wires 231, 232 set so that the first angle becomes smaller than the second one. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体器件，其封装具有不同尺寸的芯片和不同的焊盘位置并且适合共享的芯片。 解决方案：半导体器件包括芯片220，其具有引线框架的多个第一引线210，引线框架具有锯齿形指状物211，该锯齿形指状物211包括经受V形相互弯曲连接的第一和第二指状部分212,213和多个 接合焊盘222的一端连接到芯片220的一组接合焊盘222，另一端任意地连接到第一和第二指状部分212,213的一组中 引线接合的方向相对于第一和第二指状部分212,213中的一个连接的组的膨胀方向形成相对于该组的膨胀方向的第二角度的第一角度 第一和第二指状部分212,213中的哪一个未连接，接合线231,232被设置为使得第一角度变得小于第二角度。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009152517A

公开(公告)日：2009-07-09

申请号：JP2008004335

申请日：2008-01-11

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： FAN WEN-JENG

IPC: H01L23/12 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L21/565 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a substrate package structure that improves the problem of cracks of a chip or around a substrate.
SOLUTION: A substrate package structure includes: a packaging substrate which has a plurality of chip carries 110 on one surface, wherein the chip carriers are defined by intersecting a plurality of substrate cutting streets; a plurality of through-holes 130 set at the substrate cutting streets and set around the chip carriers 110; and a plurality of molding areas 140 set on another surface of the chip carriers 110, wherein the molding areas are adjacent to the through-holes 130. By means of a plurality of molding bumps formed around the chip carriers 110, the problem of cracks at the chip or around the substrate is improved.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供改善芯片或基板周围的裂纹问题的基板封装结构。 解决方案：一种衬底封装结构，包括：封装衬底，其在一个表面上具有多个芯片承载件110，其中所述芯片载体由多个基板切割街道相交限定; 设置在基板切割街道处并设置在芯片载体110周围的多个通孔130; 以及设置在芯片载体110的另一表面上的多个模制区域140，其中模制区域与通孔130相邻。通过形成在芯片载体110周围的多个模制凸起，存在着在 芯片或基板周围被改善。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008159853A

公开(公告)日：2008-07-10

申请号：JP2006347244

申请日：2006-12-25

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： HONG JIATOU ,  LU ZHAOXIANG ,  QIU ZHENGXIAN

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2225/06562

Abstract: PROBLEM TO BE SOLVED: To provide a package structure capable of improving reliability of a semiconductor package product.
SOLUTION: Provided are a plurality of first side leads 211 and a plurality of second side leads 212 of a lead frame. A plurality of first die attach strips 220 are stuck on undersurfaces of some of the group of the first-side leads 211. A first chip 230 has an active surface stuck on the group of the first die attach strips 220. A plurality of first bonding wires 251 electrically connect a single-side pad 232 to the group of the first-side leads 211 and the group of the second-side leads 212. A second chip 240 is disposed above the group of the first-side leads 211. A plurality of second bonding wires 252 electrically connect the side of the first-side leads 211 and the group of the second-side leads 212 to the second chip 240. A sealing body 260 is charged in a flow type path 221.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够提高半导体封装产品的可靠性的封装结构。 解决方案：提供引线框架的多个第一侧引线211和多个第二侧引线212。 多个第一管芯附接条220粘附在一组第一侧引线211的一些的下表面上。第一芯片230具有粘附在第一管芯附接条220组上的有效表面。多个第一接合 电线251将单侧焊盘232电连接到第一侧引线211和第二侧引线212的组。第二芯片240设置在第一侧引线211的组之上。多个 第二接合线252将第一侧引线211的侧面和第二侧引线212的一组电连接到第二芯片240.密封体260被充入流动型路径221中。 （C）2008，JPO＆INPIT

公开(公告)号：JP2012253190A

公开(公告)日：2012-12-20

申请号：JP2011124482

申请日：2011-06-02

Applicant: Powertech Technology Inc ,  力成科技股▲分▼有限公司

Inventor： SEO SU-KYOM

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L24/97 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package having more excellent side surface electromagnetic shield effect, and to provide an assembling method of the same.SOLUTION: In a semiconductor assembling method, a mother board having a board unit 213 is provided, and an alignment mark 215 for coupling to the ground is disposed at a corner of the board unit 213. A chip 220 is placed on the board unit 213. A seal 230 is formed on an upper surface 211 of the mother board to continuously cover the board unit 213 and a division line. A plurality of half-cut grooves 240 are formed along the division lines on a lower surface 212 of the mother board to pass through at least the mother board. A first electromagnetic shield layer 251 is formed and patterned on the lower surface 212 of the mother board and on a group of the half-cut grooves 240 to cover and couple with the alignment mark 215. After the seal 230 is diced individually, a second electromagnetic shield layer 252 coupled with the first electromagnetic shield layer 251 is formed on a top surface 231 and divided side surfaces 232 of the seal 230.

Abstract translation: 要解决的问题：提供具有更优异的侧面电磁屏蔽效果的半导体封装，并提供其组装方法。 解决方案：在半导体组装方法中，设置具有板单元213的母板，并且用于耦合到地的对准标记215设置在板单元213的拐角处。将芯片220放置在 板单元213.在母板的上表面211上形成密封件230，以连续地覆盖板单元213和分割线。 在母板的下表面212上沿着分割线形成多个半切槽240，以至少通过母板。 第一电磁屏蔽层251形成并形成在母板的下表面212上并在一组半切槽240上覆盖并与对准标记215相连。在密封件230被单独切割之后， 与第一电磁屏蔽层251耦合的电磁屏蔽层252形成在密封件230的顶表面231和分开的侧表面232上。（C）2013，JPO和INPIT

公开(公告)号：JP2012124487A

公开(公告)日：2012-06-28

申请号：JP2011266388

申请日：2011-12-06

Applicant: Powertech Technology Inc ,  力成科技股▲ふん▼有限公司

Inventor： JAN KUN-ZHI ,  KAKU KENGEN ,  TNEG MU-SEN

IPC: H05K13/02

CPC classification number: H01L21/67333 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a tape.SOLUTION: A tape has a main body, a mounting plate, and a side wall, and mounts at least one semiconductor package structure. The main body has at least one opening. The mounting plate can mount the semiconductor package structure, and has a plurality of housing parts. The side wall surrounds the mounting plate and is connected between the main body and the mounting plate. A lateral face of the semiconductor package structure leans against the side wall. A plurality of solder balls provided on a bottom face of the semiconductor package structure are housed in the housing parts. Thereby, the solder balls are prevented from being contacted with the mounting plate and damaged.

Abstract translation: 要解决的问题：提供磁带。 解决方案：胶带具有主体，安装板和侧壁，并且安装至少一个半导体封装结构。 主体至少有一个开口。 安装板可以安装半导体封装结构，并且具有多个壳体部件。 侧壁围绕安装板并且连接在主体和安装板之间。 半导体封装结构的侧面靠在侧壁上。 设置在半导体封装结构的底面上的多个焊料球容纳在壳体部分中。 从而防止焊球与安装板接触并损坏。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2009290182A

公开(公告)日：2009-12-10

申请号：JP2008207020

申请日：2008-08-11

Applicant: Powertech Technology Inc ,  パワーテック テクノロジー インコーポレイテッド

Inventor： CHEN CHIN-TI

IPC: H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/49575 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide lead frame package structure effectively improving the quality of a chip package. SOLUTION: This lead frame package structure includes: a plurality of leads consisting a plurality of inner leads and a plurality of outer leads; a plurality of chips installed on a portion of the plurality of inner leads; a plurality of conductive wires electrically connecting the chips to the other inner leads; a support element installed on the lower surface of the inner leads and having a recessed tank with an opening of the recessed tank directed upward; and a molding material covering the leads, chips, conductive wires and support element, and filling up the recessed tank with a portion of the outer leads and a portion of the surface of the support member exposed. The invention also includes a method for manufacturing the lead frame package structure. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供引线框封装结构，有效提高芯片封装的质量。 该引线框封装结构包括：多个引线，其包括多个内引线和多个外引线; 安装在所述多个内引线的一部分上的多个芯片; 多个导线将芯片电连接到其它内引线; 安装在所述内引线的下表面上并具有凹槽的支撑元件，所述凹槽的开口朝向上方; 以及覆盖引线，芯片，导线和支撑元件的成型材料，并且用外引线的一部分和支撑构件的表面的一部分露出来填充凹槽。 本发明还包括一种用于制造引线框架封装结构的方法。 版权所有（C）2010，JPO＆INPIT