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    COMMODITY BUYING AND SELLING SUPPORT METHOD AND SERVER
    1.
    发明专利
    COMMODITY BUYING AND SELLING SUPPORT METHOD AND SERVER 失效

    公开(公告)号：JP2002074063A

    公开(公告)日：2002-03-12

    申请号：JP2000264683

    申请日：2000-08-31

    Applicant: IBM JAPAN ,  IBM JAPAN BUSINESS LOGISTICS C ,  TOPPAN PRINTING CO LTD

    Inventor： HAGIWARA ATSUSHI ,  SATO YOSHIYUKI ,  HANAMATA TORU

    IPC: G06Q50/00 ,  G06Q30/06 ,  G06F17/60

    Abstract: PROBLEM TO BE SOLVED: To enable a buyer to quickly and fully obtain information on the commodity, and to enable a seller to more easily obtain information on the request and demand for the commodity and enlarge the business activities. SOLUTION: A control part 11, which received the inquiry information on the commodity input by the buyer transmits inquiry information to terminals of all sellers registered in a system. The control part 11 transmits reply information input by the seller to the terminal of the buyer, who has transmitted the inquiry information. Next, the control part 11 transmits the estimate request information on the commodity input by the buyer to the terminal of the seller designated by the buyer, and transmits the estimate information input by the seller to the terminal of the buyer. The control part 11 transmits the ordering information input by the buyer to the terminal of the seller, from which the estimate is adopted by the buyer.

    High-word facility for extending the number of general purpose register available to instruction
    4.
    发明专利
    High-word facility for extending the number of general purpose register available to instruction 有权
    提高可用于指导的一般用途注册号码的高字节设施

    公开(公告)号：JP2013242918A

    公开(公告)日：2013-12-05

    申请号：JP2013162972

    申请日：2013-08-06

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： DANIEL F GLINER ,  MARCEL MITRAN ,  TIMOTHY J SIEGEL

    IPC: G06F9/34

    CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/342

    Abstract: PROBLEM TO BE SOLVED: To provide new instruction functionality consistent with an existing architecture.SOLUTION: Dependency on architecture resources such as general registers is relieved, and functionality and performance of software versions employing the new instruction are improved. A computer employs a plurality of general purpose registers. Each general purpose register comprises a high order portion and a low order portion. Programs such as an operating system and applications operating in a large-capacity addressing mode, access the full general purpose registers, however programs such as applications operating in small-capacity addressing mode, only have access to a portion at a time. Instruction Opcodes, in small-capacity addressing mode, may determine which portion is accessed.

    Abstract translation: 要解决的问题：提供与现有架构一致的新指令功能。解决方案：解决了对通用寄存器等架构资源的依赖性，并提高了采用新指令的软件版本的功能和性能。 计算机采用多个通用寄存器。 每个通用寄存器包括高阶部分和低阶部分。 诸如操作系统和以大容量寻址模式运行的应用程序之类的程序访问完整的通用寄存器，然而诸如以小容量寻址模式运行的应用程序的程序只能一次访问一部分。 指令操作码在小容量寻址模式下，可以确定访问哪个部分。

    Hash collision reduction system, method and program
    5.
    发明专利
    Hash collision reduction system, method and program 有权
    HASH碰撞减少系统，方法和程序

    公开(公告)号：JP2013242539A

    公开(公告)日：2013-12-05

    申请号：JP2013081290

    申请日：2013-04-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： CASIMER M DECUSATIS ,  FABRICE JAN VERPLANKEN ,  JEAN L CALVIGNAC ,  DANIEL WIND

    IPC: G09C1/00 ,  H04L9/16

    CPC classification number: G06F17/30002 ,  G06F17/30949 ,  H04L9/00 ,  H04L9/3236 ,  H04L45/7453

    Abstract: PROBLEM TO BE SOLVED: To provide an improved computer system.SOLUTION: The system may include a controller having a computer processor. The controller reduces insertion times and/or hashing collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables, where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed, which results in change of nearly half of bits in the plurality of tables.

    Abstract translation: 要解决的问题：提供改进的计算机系统。解决方案：系统可以包括具有计算机处理器的控制器。 当与引入控制器的新组件接口时，控制器可以减少插入时间和/或散列碰撞。 该系统还可以包括通过使用多个表和每个桶的多个密钥来减少散列冲突的冲突避免装置。 该系统还可以包括与控制器通信的散列装置，以将多个密钥映射到多个表，其中散列装置使用单个散列逻辑来在一个密钥改变时提供雪崩效应，这导致 多个表中的几乎一半的位。

    Optimization of sram performance over extended voltage or process range using self-timed calibration of local clock generator
    6.
    发明专利
    Optimization of sram performance over extended voltage or process range using self-timed calibration of local clock generator 有权
    利用本地时钟发生器的自定义校准优化SRAM性能，扩展电压或过程范围

    公开(公告)号：JP2013232275A

    公开(公告)日：2013-11-14

    申请号：JP2013107770

    申请日：2013-05-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： PANG LIANG-TECK ,  JENTE BENEDICT KUANG ,  GARY D CARPENTER ,  KEVIN JOHN NOWKA

    IPC: G11C11/417 ,  G06F1/04 ,  G11C11/413 ,  H03K5/135

    CPC classification number: G11C11/417 ,  G11C7/22 ,  G11C11/419

    Abstract: PROBLEM TO BE SOLVED: To provide a method of operating a memory array such as static random-access memory (SRAM) which uses locally generated clock signals.SOLUTION: A delay circuit has a fixed delay path 12 at a lower voltage level, a level converter 36, and an adjustable delay path 14' at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to a circuit output. In an application for a local clock buffer 30 of a static random-access memory (SRAM) 32, the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns a correct output.

    Abstract translation: 要解决的问题：提供一种操作诸如使用本地生成的时钟信号的静态随机存取存储器（SRAM）的存储器阵列的方法。解决方案：延迟电路具有处于较低电压电平的固定延迟路径12， 转换器36和可调延迟路径14'处于较高电压电平。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）32的本地时钟缓冲器30的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取存取时间来校准，直到同时读取操作返回正确的输出。

    Method, computer, and computer program for speculatively optimizing code
    7.
    发明专利
    Method, computer, and computer program for speculatively optimizing code 有权
    用于规范优化代码的方法，计算机和计算机程序

    公开(公告)号：JP2013228845A

    公开(公告)日：2013-11-07

    申请号：JP2012099873

    申请日：2012-04-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： ISHIZAKI KAZUAKI

    IPC: G06F9/45

    CPC classification number: G06F8/443

    Abstract: PROBLEM TO BE SOLVED: To prevent invalidation when the invalidation of a compiled code is not required.SOLUTION: A technique for speculatively optimizing a code includes: searching one or more dictionaries in predetermined order; extracting a value associated with a symbol name from the dictionaries by using the symbol name as a key; performing optimization to replace a symbol in the code with the value; compiling the code to be compiled including some or all of the optimized code; after the compilation, in response to detection of a change related to one of the dictionaries, comparing a rank m of the dictionary having the detected change in the predetermined order to a rank n of the dictionary having the extracted value; and invalidating the optimized code in the compiled code associated with the dictionary having the detected change in accordance with a result of the comparison of the ranks and with a type of the change.

    Abstract translation: 要解决的问题：当不需要编译代码的无效时，防止无效。解决方案：用于推测优化代码的技术包括：按预定顺序搜索一个或多个字典; 通过使用符号名称作为关键字从字典中提取与符号名称相关联的值; 执行优化以用该值替换代码中的符号; 编译要编译的代码，包括一些或全部优化的代码; 在编译之后，响应于检测到与其中一个字典相关的改变，将具有预定顺序的检测到的改变的字典的秩m与具有提取的值的字典的秩n进行比较; 并根据等级的比较结果与变化的类型，使具有检测到的改变的字典相关联的编译代码中的优化代码无效。

    Code conversion method, program and system
    9.
    发明专利
    Code conversion method, program and system 有权
    代码转换方法，程序和系统

    公开(公告)号：JP2013222303A

    公开(公告)日：2013-10-28

    申请号：JP2012093355

    申请日：2012-04-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： TOZAWA MASAHIKO ,  KOSEKI SATOSHI

    IPC: G06F9/45

    CPC classification number: G06F8/51

    Abstract: PROBLEM TO BE SOLVED: To quicken the execution of the code of the processing of an iterator.SOLUTION: Data conversion is expressed with generator conversion on an intermediate language having a generator, and optimized by a compiler. Thus, the data conversion is expressed with the generator conversion. Then, the in-lining rewriting of the generator is applied on the intermediate language. When a generator g is consumed in the form of a for(x:g){e} sentence, the in-lining of the generator is achieved by replacing the "for(x:g){e}" itself (by performing the in-lining of a generation side code into a consumption side code) with "the appearance of yield in the definition of g is replaced with e (by performing the in-lining of the consumption side code into the generation side code)".

    Abstract translation: 要解决的问题：加快​​迭代器处理代码的执行。解决方案：数据转换用具有生成器的中间语言的生成器转换表示，并由编译器优化。 因此，数据转换用发生器转换表示。 然后，生成器的内衬重写应用于中间语言。 当以（x：g）{e}语句的形式消耗发电机g时，发电机的内衬是通过将“for（x：g）{e}”本身（通过执行 将代码代码内置到消费方代码中），其中“g的定义中的收益的出现被e（通过执行消费侧代码的内插代入代码代码）”来代替。

    Method, program and system for generating rdf expression
    10.
    发明专利
    Method, program and system for generating rdf expression 有权
    用于生成RDF表达的方法，程序和系统

    公开(公告)号：JP2013218554A

    公开(公告)日：2013-10-24

    申请号：JP2012089261

    申请日：2012-04-10

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： NAKAMURA HIROAKI ,  TAI HIDEKI ,  AMANO SHUNICHI ,  MIYASHITA TAKASHI

    IPC: G06F12/00

    CPC classification number: G06F17/30289

    Abstract: PROBLEM TO BE SOLVED: To reduce access frequency to an existing tool in converting data into RDF through the access to the existing tool.SOLUTION: A set of IDs for data of an existing tool is embodied as a parameter; a bulk access template is prepared that acquires a plurality of data pieces one time, or a few times at most; and access to the existing tool is provided through the bulk access template. The bulk access template is prepared for each type of data to be acquired. Next, the template is instantiated based on a requested URI, and entries that correspond to an operating table are filled in by executing the instantiated template. When an RDF expression is requested for the URI of the template that is the same as one already accessed, the entries are already in the operating table, so that the RDF expression can be generated without generating access to the existing tool.

    Abstract translation: 要解决的问题：减少通过访问现有工具将数据转换为RDF的现有工具的访问频率。解决方案：现有工具的数据的一组ID被体现为参数; 准备一个批次访问模板，其中获取多个数据片段最多一次或几次; 并通过批量访问模板提供对现有工具的访问。 批量访问模板是为每种待获取的数据准备的。 接下来，基于请求的URI来实例化模板，并且通过执行实例化的模板来填充与操作表相对应的条目。 当为与已访问的模板相同的模板的URI请求RDF表达式时，这些条目已经在操作表中，因此可以生成RDF表达式而不生成对现有工具的访问。

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