公开(公告)号：US20170352612A1

公开(公告)日：2017-12-07

申请号：US15435951

申请日：2017-02-17

Applicant: SK hynix Inc.

Inventor： Ki Jun SUNG ,  Jong Hoon KIM ,  Han Jun BAE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

公开(公告)号：US20160064359A1

公开(公告)日：2016-03-03

申请号：US14935105

申请日：2015-11-06

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.

Abstract translation: 提供堆栈包。 堆叠封装包括第一芯片，其构造成包括具有顶表面和底表面的第一芯片主体，第一穿透电极穿过第一芯片主体的绝缘层，以及设置在第一芯片主体的底表面上的绝缘层， 设置在第一芯片主体的上表面上，第二芯片构造成包括具有顶表面和底表面的第二芯片主体，以及设置在第二芯片主体的顶表面上的第二凸块。 第一芯片和第二芯片被垂直堆叠，使得第二芯片主体的顶表面直接附接到第一绝缘层，并且第二芯片的第二凸块穿透第一芯片的第一绝缘层以刺穿第一芯片主体的第一穿透电极 第一个芯片。

公开(公告)号：US20180019188A1

公开(公告)日：2018-01-18

申请号：US15718319

申请日：2017-09-28

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE ,  Chan Woo JEONG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/4985 ,  H01L23/293 ,  H01L23/298 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32238

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

公开(公告)号：US20150028473A1

公开(公告)日：2015-01-29

申请号：US14245618

申请日：2014-04-04

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 提供堆栈包。 堆叠包装包括第一芯片和第二芯片。 第一芯片包括第一芯片体，穿过第一芯片体的第一穿透电极和设置在第一芯片主体的底表面上的绝缘层。 第二芯片包括设置在第二芯片主体的顶表面上的第二芯片体和凸块。 第一和第二芯片垂直堆叠，使得凸块穿透绝缘层以刺穿第一通孔，第二芯片体的顶表面直接接触绝缘层。 还提供了相关的制造方法，电子系统和存储卡。

公开(公告)号：US20220037304A1

公开(公告)日：2022-02-03

申请号：US17156239

申请日：2021-01-22

Applicant: SK hynix Inc.

Inventor： Ju Il EOM ,  Han Jun BAE ,  Seung Yeop LEE

IPC: H01L25/18 ,  H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.

公开(公告)号：US20170148708A1

公开(公告)日：2017-05-25

申请号：US15068877

申请日：2016-03-14

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE ,  Chan Woo JEONG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/4985 ,  H01L23/293 ,  H01L23/298 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32238

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

公开(公告)号：US20210366847A1

公开(公告)日：2021-11-25

申请号：US16991683

申请日：2020-08-12

Applicant: SK hynix Inc.

Inventor： Ju Il EOM ,  Jin Kyoung PARK ,  Han Jun BAE

IPC: H01L23/64 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.

公开(公告)号：US20160254251A1

公开(公告)日：2016-09-01

申请号：US14850385

申请日：2015-09-10

Applicant: SK hynix Inc.

Inventor： Han Jun BAE ,  Won Duck JUNG

IPC: H01L25/065

CPC classification number: H01L29/0657 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/10158 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.

Abstract translation: 半导体器件包括衬底，设置在衬底的表面上的弹性缓冲层，布置在弹性缓冲层的第一表面上的布线图案，以及布置在弹性缓冲层的背离弹性缓冲层的第二表面上的半导体芯片 弹性缓冲层的第一表面。 半导体芯片包括形成在面向弹性缓冲层的表面上的沟槽。 互连构件被设置为将弹性缓冲层电连接到衬底。 每个互连构件的一端电连接到一个布线图案，另一端电连接到基板。

公开(公告)号：US20160211188A1

公开(公告)日：2016-07-21

申请号：US14808596

申请日：2015-07-24

Applicant: SK hynix Inc.

Inventor： Dae Woong LEE ,  Tae Min KANG ,  Han Jun BAE

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/293 ,  H01L21/563 ,  H01L23/296 ,  H01L23/3142 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92247 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/0715

Abstract: A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.

Abstract translation: 半导体封装包括设置在封装基板上以具有梯形横截面图的粘合构件，以及设置在粘合构件上并通过粘合构件附接到封装基板的半导体芯片。 半导体芯片具有面向第一表面的第一表面和第二表面，并且半导体芯片的第二表面接触粘合构件。 半导体芯片包括附着到第二表面并与封装衬底隔开的张力补充图案。

公开(公告)号：US20170033081A1

公开(公告)日：2017-02-02

申请号：US14924884

申请日：2015-10-28

Applicant: SK hynix Inc.

Inventor： Je Sik YOO ,  Jong Hyun KIM ,  Yo Seph JEONG ,  Han Jun BAE

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stack package may include a substrate, and a first semiconductor chip mounted over the substrate. The stack package may include a support member disposed over the substrate and the first semiconductor chip, and spaced apart from the substrate and the first semiconductor chip. The stack package may include a plurality of second semiconductor chips stacked over the support member.

Abstract translation: 堆叠封装可以包括衬底和安装在衬底上的第一半导体芯片。 堆叠封装可以包括设置在衬底和第一半导体芯片上并且与衬底和第一半导体芯片间隔开的支撑构件。 堆叠封装可以包括堆叠在支撑构件上的多个第二半导体芯片。