公开(公告)号：US20240315023A1

公开(公告)日：2024-09-19

申请号：US18489451

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5223 ,  H10B41/27

Abstract: Disclosed are semiconductor devices which may include a substrate having first and second regions, a stack structure including electrode patterns and dielectric patterns, channels vertically penetrating the stack structure on the first region, a planarized dielectric layer covering the stack structure, and wiring patterns on the planarized dielectric layer. The dielectric pattern includes a first dielectric pattern on the first region, and a second dielectric pattern on the second region. The second dielectric pattern includes a first sub-dielectric pattern and a second sub-dielectric pattern. A dielectric constant of the first sub-dielectric patterns is greater than that of the first dielectric patterns and that of the second sub-dielectric patterns.

公开(公告)号：US20250167115A1

公开(公告)日：2025-05-22

申请号：US18925771

申请日：2024-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo GU ,  Bumkyu KANG ,  Ahreum LEE ,  Junhyoung KIM ,  Jiwon KIM ,  Sukkang SUNG

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H10B12/00 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a peripheral circuit structure first bonding pads connected to peripheral circuits on a semiconductor substrate; and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure may include a separation structure penetrating a stack structure, vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer. The stack structure may include interlayer dielectric layers and conductive patterns that are vertically alternately stacked. The separation structure may include a stop pattern on a dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. The upper via may connect to the source conductive pattern on the stop pattern.

公开(公告)号：US20240224514A1

公开(公告)日：2024-07-04

申请号：US18498673

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H10B41/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: An integrated circuit device includes a substrate including a memory cell area and a connection area, a gate stack including a plurality of gate electrodes apart from each other in a vertical direction on the substrate, a plurality of gate connection openings arranged in the connection area to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings, a plurality of gate connection structures respectively covering at least inner side surfaces of the plurality of gate connection openings, each of the plurality of gate connection structures being connected with the one gate electrode, and a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures.

公开(公告)号：US20220149072A1

公开(公告)日：2022-05-12

申请号：US17375273

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo GU ,  Bumkyu KANG ,  Sungmin HWANG

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

公开(公告)号：US20240038660A1

公开(公告)日：2024-02-01

申请号：US18197283

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Jaeho KIM ,  Sukkang SUNG

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/0652

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region. A memory stack includes a plurality of word lines extending in the memory cell region and the connection region in a horizontal direction that is parallel with an upper surface of the substrate. The plurality of word lines overlaps with each other in a vertical direction. A support is in the connection region and positioned at a side of the memory stack. The support includes a plurality of steps. A plurality of pad parts is on a top surface of the support. A plurality of contact plugs passes through at least some of the plurality of word lines in the vertical direction. The plurality of contact plugs directly contacts the plurality of pad parts for electrical connection therewith.

公开(公告)号：US20230378083A1

公开(公告)日：2023-11-23

申请号：US18172534

申请日：2023-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.