公开(公告)号：US20120270389A1

公开(公告)日：2012-10-25

申请号：US13090312

申请日：2011-04-20

Applicant: Chun-Ling LIN ,  Chin-Fu Lin ,  Chi-Mao Hsu

Inventor： Chun-Ling LIN ,  Chin-Fu Lin ,  Chi-Mao Hsu

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/2855 ,  C23C14/0641 ,  H01L21/31144 ,  H01L21/7681

Abstract: A method for manufacturing a metal nitride layer including the following steps is provided. Firstly, a substrate is provided. Then, a physical vapor deposition process is performed at a temperature between 210° C. and 390° C. to form a metal nitride layer on the substrate. Also, the physical vapor deposition process can be performed on a pressure between 21 mTorr and 91 mTorr. The method can be used in the manufacturing process of an interconnection structure for decreasing the film stress of the metal nitride layer. Therefore, the interconnection structure can be prevented from line distortion and film collapse.

Abstract translation: 提供了包括以下步骤的金属氮化物层的制造方法。 首先，提供基板。 然后，在210℃和390℃之间的温度下进行物理气相沉积工艺，以在衬底上形成金属氮化物层。 此外，物理气相沉积工艺可以在21mTorr和91mTorr之间的压力下进行。 该方法可用于互连结构的制造过程中，以降低金属氮化物层的膜应力。 因此，可以防止互连结构线路变形和薄膜塌陷。

公开(公告)号：US20120241863A1

公开(公告)日：2012-09-27

申请号：US13052338

申请日：2011-03-21

Applicant: Teng-Chun TSAI ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

Inventor： Teng-Chun TSAI ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。 高k金属栅极形成在基板和鳍状通道上。 制造鳍式场效应晶体管结构的工艺包括以下步骤。 首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。 通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。 在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。 然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

公开(公告)号：US08067806B2

公开(公告)日：2011-11-29

申请号：US12557535

申请日：2009-09-11

Applicant: Chun-Hsien Lin ,  Chin-Fu Lin

Inventor： Chun-Hsien Lin ,  Chin-Fu Lin

IPC: H01L21/70

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Gate structures of CMOS device and the method for manufacturing the same are provided. A substrate having an NMOS region, a PMOS region, and a work function modulation layer disposed on the NMOS region and the PMOS region is provided. A nitrogen doping process is performed to dope nitrogen into a portion of the work function modulation layer disposed on the PMOS region so as to form an N-rich work function modulation layer disposed on the PMOS region. A nonmetallic conductive layer is formed blanketly covering the work function modulation layer and the N-rich work function modulation layer. A portion of the nonmetallic conductive layer, the work function modulation layer, and the N-rich work function modulation layer is removed to form a first gate in the NMOS region and a second gate in the PMOS region.

Abstract translation: 提供了CMOS器件的栅极结构及其制造方法。 提供了具有NMOS区域，PMOS区域和设置在NMOS区域和PMOS区域上的功函数调制层的衬底。 执行氮掺杂工艺以将氮掺杂到设置在PMOS区上的功函数调制层的一部分中，以形成设置在PMOS区上的富N功函数调制层。 非金属导电层被形成为覆盖功函数调制层和富N功函数调制层。 去除部分非金属导电层，功函数调制层和富N功函数调制层，以在NMOS区域中形成第一栅极，在PMOS区域中形成第二栅极。

公开(公告)号：US20110062524A1

公开(公告)日：2011-03-17

申请号：US12557535

申请日：2009-09-11

Applicant: Chun-Hsien Lin ,  Chin-Fu Lin

Inventor： Chun-Hsien Lin ,  Chin-Fu Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Gate structures of CMOS device and the method for manufacturing the same are provided. A substrate having an NMOS region, a PMOS region, and a work function modulation layer disposed on the NMOS region and the PMOS region is provided. A nitrogen doping process is performed to dope nitrogen into a portion of the work function modulation layer disposed on the PMOS region so as to form an N-rich work function modulation layer disposed on the PMOS region. A nonmetallic conductive layer is formed blanketly covering the work function modulation layer and the N-rich work function modulation layer. A portion of the nonmetallic conductive layer, the work function modulation layer, and the N-rich work function modulation layer is removed to form a first gate in the NMOS region and a second gate in the PMOS region.

Abstract translation: 提供了CMOS器件的栅极结构及其制造方法。 提供了具有NMOS区域，PMOS区域和设置在NMOS区域和PMOS区域上的功函数调制层的衬底。 执行氮掺杂工艺以将氮掺杂到设置在PMOS区上的功函数调制层的一部分中，以形成设置在PMOS区上的富N功函数调制层。 非金属导电层被形成为覆盖功函数调制层和富N功函数调制层。 去除部分非金属导电层，功函数调制层和富N功函数调制层，以在NMOS区域中形成第一栅极，在PMOS区域中形成第二栅极。

公开(公告)号：US20060144337A1

公开(公告)日：2006-07-06

申请号：US10905471

申请日：2005-01-06

Applicant: Hsien-Che Teng ,  Chin-Fu Lin ,  Chun-Hao Chu

Inventor： Hsien-Che Teng ,  Chin-Fu Lin ,  Chun-Hao Chu

IPC: C23C16/00

CPC classification number: C23C14/50

Abstract: A heater for heating a wafer is applied in a process chamber. The heater has an upper surface for positioning a wafer to heat the wafer, wherein a connection area of the upper surface and the wafer is less than the area of the wafer when the wafer is positioned on the upper surface of the heater.

Abstract translation: 用于加热晶片的加热器被施加在处理室中。 加热器具有用于定位晶片以加热晶片的上表面，其中当晶片位于加热器的上表面上时，上表面和晶片的连接区域小于晶片的面积。

公开(公告)号：US20060102284A1

公开(公告)日：2006-05-18

申请号：US10904541

申请日：2004-11-15

Applicant: Hsien-Che Teng ,  Chin-Fu Lin ,  Jen-Yuan Wu

Inventor： Hsien-Che Teng ,  Chin-Fu Lin ,  Jen-Yuan Wu

IPC: H01L21/306

CPC classification number: H01L21/67017 ,  H01L21/67778

Abstract: A semiconductor manufacturing equipment comprising a canopy, a semiconductor processing device, a load port, a robot arm or a transferring device, an air vent, and a chemical filter to remove chemical substance in the air. A HEPA or ULPA filter may be included to filter off particulates. The load port may have a standardized mechanical interface (SMIF) suitable for SMIF pods. In the case that the semiconductor processing device is a copper processing tool, an advantage of preventing copper from corrosion is attained in the present invention by removing chemical substance.

Abstract translation: 一种半导体制造设备，包括冠层，半导体处理装置，负载端口，机器人手臂或转移装置，通风口和化学过滤器，以去除空气中的化学物质。 可以包括HEPA或ULPA过滤器以过滤掉颗粒物。 负载端口可以具有适用于SMIF盒的标准化机械接口（SMIF）。 在半导体处理装置是铜加工工具的情况下，通过除去化学物质，可以在本发明中获得防止铜腐蚀的优点。